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fcoopertitrini
fcooperti
authored and
trini
committed
am43xx: Tune the system to avoid DSS underflows
* This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
1 parent 2c95211 commit 8038b49

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5 files changed

+111
-10
lines changed

5 files changed

+111
-10
lines changed

‎arch/arm/cpu/armv7/am33xx/ddr.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,18 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
9494
writel(regs->emif_rd_wr_exec_thresh,
9595
&emif_reg[nr]->emif_rd_wr_exec_thresh);
9696

97+
/*
98+
* for most SOCs these registers won't need to be changed so only
99+
* write to these registers if someone explicitly has set the
100+
* register's value.
101+
*/
102+
if(regs->emif_cos_config) {
103+
writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
104+
writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
105+
writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
106+
writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
107+
}
108+
97109
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
98110
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
99111
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);

‎arch/arm/include/asm/arch-am33xx/cpu.h‎

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -489,6 +489,12 @@ struct ctrl_stat {
489489
#define OMAP_GPIO_SETDATAOUT 0x0194
490490

491491
/* Control Device Register */
492+
493+
/* Control Device Register */
494+
#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
495+
#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
496+
#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
497+
492498
struct ctrl_dev {
493499
unsigned int deviceid; /* offset 0x00 */
494500
unsigned int resv1[7];
@@ -502,10 +508,25 @@ struct ctrl_dev {
502508
unsigned int macid1h; /* offset 0x3c */
503509
unsigned int resv4[4];
504510
unsigned int miisel; /* offset 0x50 */
505-
unsigned int resv5[106];
511+
unsigned int resv5[7];
512+
unsigned int mreqprio_0; /* offset 0x70 */
513+
unsigned int mreqprio_1; /* offset 0x74 */
514+
unsigned int resv6[97];
506515
unsigned int efuse_sma; /* offset 0x1FC */
507516
};
508517

518+
/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
519+
#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
520+
#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
521+
#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
522+
523+
struct l3f_cfg_bwlimiter {
524+
u32 padding0[2];
525+
u32 modena_init0_bw_fractional;
526+
u32 modena_init0_bw_integer;
527+
u32 modena_init0_watermark_0;
528+
};
529+
509530
/* gmii_sel register defines */
510531
#define GMII1_SEL_MII 0x0
511532
#define GMII1_SEL_RMII 0x1

‎arch/arm/include/asm/arch-am33xx/hardware_am43xx.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@
1313

1414
/* Module base addresses */
1515

16+
/* L3 Fast Configuration Bandwidth Limiter Base Address */
17+
#define L3F_CFG_BWLIMITER 0x44005200
18+
1619
/* UART Base Address */
1720
#define UART0_BASE 0x44E09000
1821

‎arch/arm/include/asm/emif.h‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -642,11 +642,16 @@ struct emif_reg_struct {
642642
u32 emif_ddr_phy_ctrl_1;
643643
u32 emif_ddr_phy_ctrl_1_shdw;
644644
u32 emif_ddr_phy_ctrl_2;
645-
u32 padding7[12];
645+
u32 padding7[4];
646+
u32 emif_prio_class_serv_map;
647+
u32 emif_connect_id_serv_1_map;
648+
u32 emif_connect_id_serv_2_map;
649+
u32 padding8[5];
646650
u32 emif_rd_wr_exec_thresh;
647-
u32 padding8[7];
651+
u32 emif_cos_config;
652+
u32 padding9[6];
648653
u32 emif_ddr_phy_status[21];
649-
u32 padding9[27];
654+
u32 padding10[27];
650655
u32 emif_ddr_ext_phy_ctrl_1;
651656
u32 emif_ddr_ext_phy_ctrl_1_shdw;
652657
u32 emif_ddr_ext_phy_ctrl_2;
@@ -1137,6 +1142,10 @@ struct emif_regs {
11371142
u32 emif_rd_wr_lvl_rmp_ctl;
11381143
u32 emif_rd_wr_lvl_ctl;
11391144
u32 emif_rd_wr_exec_thresh;
1145+
u32 emif_prio_class_serv_map;
1146+
u32 emif_connect_id_serv_1_map;
1147+
u32 emif_connect_id_serv_2_map;
1148+
u32 emif_cos_config;
11401149
};
11411150

11421151
struct lpddr2_mr_regs {

‎board/ti/am43xx/board.c‎

Lines changed: 62 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -157,12 +157,16 @@ const struct emif_regs emif_regs_lpddr2 = {
157157
.emif_rd_wr_lvl_rmp_ctl = 0x0,
158158
.emif_rd_wr_lvl_ctl = 0x0,
159159
.emif_ddr_phy_ctlr_1 = 0x0E084006,
160-
.emif_rd_wr_exec_thresh = 0x00000405,
160+
.emif_rd_wr_exec_thresh = 0x80000405,
161161
.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
162162
.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
163163
.emif_ddr_ext_phy_ctrl_3 = 0x00500050,
164164
.emif_ddr_ext_phy_ctrl_4 = 0x00500050,
165-
.emif_ddr_ext_phy_ctrl_5 = 0x00500050
165+
.emif_ddr_ext_phy_ctrl_5 = 0x00500050,
166+
.emif_prio_class_serv_map = 0x80000001,
167+
.emif_connect_id_serv_1_map = 0x80000094,
168+
.emif_connect_id_serv_2_map = 0x00000000,
169+
.emif_cos_config = 0x000FFFFF
166170
};
167171

168172
const u32 ext_phy_ctrl_const_base_lpddr2[] = {
@@ -217,7 +221,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
217221
.emif_rd_wr_lvl_rmp_win = 0x0,
218222
.emif_rd_wr_lvl_rmp_ctl = 0x0,
219223
.emif_rd_wr_lvl_ctl = 0x0,
220-
.emif_rd_wr_exec_thresh = 0x00000405
224+
.emif_rd_wr_exec_thresh = 0x80000405,
225+
.emif_prio_class_serv_map = 0x80000001,
226+
.emif_connect_id_serv_1_map = 0x80000094,
227+
.emif_connect_id_serv_2_map = 0x00000000,
228+
.emif_cos_config = 0x000FFFFF
221229
};
222230

223231
/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
@@ -236,7 +244,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
236244
.emif_ddr_ext_phy_ctrl_3 = 0x00000091,
237245
.emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
238246
.emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
239-
.emif_rd_wr_exec_thresh = 0x00000405
247+
.emif_rd_wr_exec_thresh = 0x80000405,
248+
.emif_prio_class_serv_map = 0x80000001,
249+
.emif_connect_id_serv_1_map = 0x80000094,
250+
.emif_connect_id_serv_2_map = 0x00000000,
251+
.emif_cos_config = 0x000FFFFF
240252
};
241253

242254
/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
@@ -255,7 +267,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = {
255267
.emif_ddr_ext_phy_ctrl_3 = 0x00000091,
256268
.emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
257269
.emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
258-
.emif_rd_wr_exec_thresh = 0x00000405
270+
.emif_rd_wr_exec_thresh = 0x80000405,
271+
.emif_prio_class_serv_map = 0x80000001,
272+
.emif_connect_id_serv_1_map = 0x80000094,
273+
.emif_connect_id_serv_2_map = 0x00000000,
274+
.emif_cos_config = 0x000FFFFF
259275
};
260276

261277
static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
@@ -277,7 +293,11 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
277293
.emif_rd_wr_lvl_rmp_win = 0x0,
278294
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
279295
.emif_rd_wr_lvl_ctl = 0x00000000,
280-
.emif_rd_wr_exec_thresh = 0x00000000,
296+
.emif_rd_wr_exec_thresh = 0x80000000,
297+
.emif_prio_class_serv_map = 0x80000001,
298+
.emif_connect_id_serv_1_map = 0x80000094,
299+
.emif_connect_id_serv_2_map = 0x00000000,
300+
.emif_cos_config = 0x000FFFFF
281301
};
282302

283303
const u32 ext_phy_ctrl_const_base_ddr3[] = {
@@ -587,8 +607,44 @@ void sdram_init(void)
587607

588608
int board_init(void)
589609
{
610+
struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
611+
u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
612+
modena_init0_bw_integer, modena_init0_watermark_0;
613+
590614
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
591615

616+
/* Clear all important bits for DSS errata that may need to be tweaked*/
617+
mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
618+
MREQPRIO_0_SAB_INIT0_MASK;
619+
620+
mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
621+
622+
modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
623+
BW_LIMITER_BW_FRAC_MASK;
624+
625+
modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
626+
BW_LIMITER_BW_INT_MASK;
627+
628+
modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
629+
BW_LIMITER_BW_WATERMARK_MASK;
630+
631+
/* Setting MReq Priority of the DSS*/
632+
mreqprio_0 |= 0x77;
633+
634+
/*
635+
* Set L3 Fast Configuration Register
636+
* Limiting bandwith for ARM core to 700 MBPS
637+
*/
638+
modena_init0_bw_fractional |= 0x10;
639+
modena_init0_bw_integer |= 0x3;
640+
641+
writel(mreqprio_0, &cdev->mreqprio_0);
642+
writel(mreqprio_1, &cdev->mreqprio_1);
643+
644+
writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
645+
writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
646+
writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
647+
592648
return 0;
593649
}
594650

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