From ac3ed87906ff62fe9d374bd284cb15702994c6de Mon Sep 17 00:00:00 2001 From: rezado <1908819406@qq.com> Date: Wed, 26 Aug 2026 14:14:36 +0800 Subject: [PATCH 1/2] fix(dts): align isa extention with rva23 --- ...gshan-fpga-noAIA-2hart-mem16g-novec.dts.in | 16 +- ...ngshan-fpga-noAIA-2hart-mem8g-novec.dts.in | 16 +- dts/xiangshan-fpga-noAIA-32hart-mem64g.dts.in | 256 +++++++++--------- dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in | 8 +- dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in | 5 +- dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in | 8 +- dts/xiangshan-fpga-noAIA-mem24g.dts.in | 8 +- dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in | 8 +- dts/xiangshan-fpga-noAIA-mem64g.dts.in | 8 +- dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in | 8 +- dts/xiangshan-fpga-noAIA-mem8g.dts.in | 8 +- dts/xiangshan-fpga-noAIA-novec.dts.in | 8 +- dts/xiangshan-fpga-noAIA.dts.in | 8 +- scripts/generate-xiangshan-multihart-dts.py | 9 +- 14 files changed, 188 insertions(+), 186 deletions(-) diff --git a/dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in b/dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in index e964dd8..9ce6c29 100644 --- a/dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-2hart-mem16g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -103,7 +103,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -116,10 +116,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in b/dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in index fa5912f..2ad9253 100644 --- a/dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-2hart-mem8g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -103,7 +103,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdch_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -116,10 +116,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-32hart-mem64g.dts.in b/dts/xiangshan-fpga-noAIA-32hart-mem64g.dts.in index cd266bd..8b509ea 100644 --- a/dts/xiangshan-fpga-noAIA-32hart-mem64g.dts.in +++ b/dts/xiangshan-fpga-noAIA-32hart-mem64g.dts.in @@ -36,7 +36,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -49,10 +49,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -75,7 +75,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -88,10 +88,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -114,7 +114,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -127,10 +127,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -153,7 +153,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -166,10 +166,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -192,7 +192,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -205,10 +205,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -231,7 +231,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -244,10 +244,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -270,7 +270,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -283,10 +283,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -309,7 +309,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -322,10 +322,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -348,7 +348,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -361,10 +361,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -387,7 +387,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -400,10 +400,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -426,7 +426,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -439,10 +439,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -465,7 +465,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -478,10 +478,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -504,7 +504,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -517,10 +517,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -543,7 +543,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -556,10 +556,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -582,7 +582,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -595,10 +595,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -621,7 +621,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -634,10 +634,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -660,7 +660,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -673,10 +673,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -699,7 +699,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -712,10 +712,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -738,7 +738,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -751,10 +751,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -777,7 +777,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -790,10 +790,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -816,7 +816,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -829,10 +829,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -855,7 +855,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -868,10 +868,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -894,7 +894,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -907,10 +907,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -933,7 +933,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -946,10 +946,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -972,7 +972,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -985,10 +985,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1011,7 +1011,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1024,10 +1024,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1050,7 +1050,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1063,10 +1063,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1089,7 +1089,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1102,10 +1102,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1128,7 +1128,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1141,10 +1141,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1167,7 +1167,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1180,10 +1180,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1206,7 +1206,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1219,10 +1219,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", @@ -1245,7 +1245,7 @@ riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -1258,10 +1258,10 @@ "sspm", "ssstateen", "ssstrict", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in index 59eccfc..60b9a00 100644 --- a/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in index 81b1da0..1c4e2a5 100644 --- a/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in @@ -24,11 +24,12 @@ reg = <0>; status = "okay"; mmu-type = "riscv,sv48"; - riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", - "smstateen", "sscofpmf", "sstc", "zicntr", "zihpm", + "smstateen", "sscofpmf", "sstc", "zaamo", "zalrsc", "zcd", + "zicbom", "zicbop", "zicboz", "zicntr", "zihpm", "svpbmt", "sdtrig", "smcsrind", "sscsrind", "svade"; intc_cpu0: interrupt-controller { diff --git a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in index b688437..6a36adf 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem24g.dts.in b/dts/xiangshan-fpga-noAIA-mem24g.dts.in index ca23fff..2fda82b 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in index 46a081f..7f3359d 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem64g.dts.in b/dts/xiangshan-fpga-noAIA-mem64g.dts.in index 51b4741..974e7f3 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in index db76ca8..e9563b2 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-mem8g.dts.in b/dts/xiangshan-fpga-noAIA-mem8g.dts.in index 6e4a902..8030fe0 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA-novec.dts.in b/dts/xiangshan-fpga-noAIA-novec.dts.in index 39888f9..b2cf397 100644 --- a/dts/xiangshan-fpga-noAIA-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/dts/xiangshan-fpga-noAIA.dts.in b/dts/xiangshan-fpga-noAIA.dts.in index f9699c8..2efb160 100644 --- a/dts/xiangshan-fpga-noAIA.dts.in +++ b/dts/xiangshan-fpga-noAIA.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", @@ -56,10 +56,10 @@ "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", - "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", - "zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", - "zic64b", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", diff --git a/scripts/generate-xiangshan-multihart-dts.py b/scripts/generate-xiangshan-multihart-dts.py index fd889f2..2e8b332 100755 --- a/scripts/generate-xiangshan-multihart-dts.py +++ b/scripts/generate-xiangshan-multihart-dts.py @@ -5,7 +5,8 @@ MULTIHART_RISCV_ISA = ( - "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_" + "rv64imafdcvh_smstateen_sscofpmf_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_" + "zicntr_zihpm_svpbmt_" "sdtrig_smcsrind_sscsrind_svade" ) MULTIHART_CPU_ISA_PROPERTIES = f"""\ @@ -22,10 +23,10 @@ \t\t\t\t"sspm", "ssstateen", "ssstrict", \t\t\t\t"sstvala", "sstvecd", "ssu64xl", "supm", \t\t\t\t"sv39", "sv48", "svade", "svbare", "svinval", -\t\t\t\t"svnapot", "svpbmt", "za64rs", "zacas", "zawrs", +\t\t\t\t"svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", \t\t\t\t"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", -\t\t\t\t"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin", -\t\t\t\t"zic64b", +\t\t\t\t"zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", +\t\t\t\t"zic64b", "zicbom", "zicbop", "zicboz", \t\t\t\t"ziccamoa", "ziccif", "zicclsm", "ziccrse", \t\t\t\t"zicntr", "zicond", "zicsr", "zifencei", \t\t\t\t"zihintntl", "zihintpause", "zihpm", "zimop", From 42966c75f8af3e60490056cd60db9d4f8a2d3108 Mon Sep 17 00:00:00 2001 From: rezado <1908819406@qq.com> Date: Wed, 26 Aug 2026 14:28:39 +0800 Subject: [PATCH 2/2] fix(dts): remove v for all novec and fix 16gb dts --- dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in | 2 +- dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in | 21 ++++++++++++++++--- dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in | 2 +- dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in | 2 +- dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in | 2 +- dts/xiangshan-fpga-noAIA-novec.dts.in | 2 +- 6 files changed, 23 insertions(+), 8 deletions(-) diff --git a/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in index 60b9a00..a155f16 100644 --- a/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem128g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", diff --git a/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in index 1c4e2a5..87bba42 100644 --- a/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem16g-novec.dts.in @@ -28,9 +28,24 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", - "smstateen", "sscofpmf", "sstc", "zaamo", "zalrsc", "zcd", - "zicbom", "zicbop", "zicboz", "zicntr", "zihpm", - "svpbmt", "sdtrig", "smcsrind", "sscsrind", "svade"; + "sdtrig", "sha", "shcounterenw", "shgatpa", + "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", + "shvstvecd", "smcsrind", "smdbltrp", + "smmpm", "smnpm", "smstateen", + "ss1p13", "ssccptr", "sscofpmf", + "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", + "sspm", "ssstateen", "ssstrict", "sstc", + "sstvala", "sstvecd", "ssu64xl", "supm", + "sv39", "sv48", "svade", "svbare", "svinval", + "svnapot", "svpbmt", "za64rs", "zaamo", "zalrsc", "zacas", "zawrs", + "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", + "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfh", "zfhmin", + "zic64b", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "ziccrse", + "zicntr", "zicond", "zicsr", "zifencei", + "zihintntl", "zihintpause", "zihpm", "zimop", + "zkn", "zknd", "zkne", "zknh", "zksed", + "zksh", "zkt"; intc_cpu0: interrupt-controller { #interrupt-cells = <1>; diff --git a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in index 6a36adf..67384d2 100644 --- a/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem24g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", diff --git a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in index 7f3359d..836423a 100644 --- a/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem64g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", diff --git a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in index e9563b2..fb5c4d3 100644 --- a/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-mem8g-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", diff --git a/dts/xiangshan-fpga-noAIA-novec.dts.in b/dts/xiangshan-fpga-noAIA-novec.dts.in index b2cf397..733d9c4 100644 --- a/dts/xiangshan-fpga-noAIA-novec.dts.in +++ b/dts/xiangshan-fpga-noAIA-novec.dts.in @@ -43,7 +43,7 @@ * workload template while using the FPGA board interrupt/peripheral * map below. */ - riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; + riscv,isa = "rv64imafdch_smstateen_sscofpmf_sstc_zaamo_zalrsc_zcd_zicbom_zicbop_zicboz_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h",