drivers: spi: siwx91x: Fix use of GSPI_DATA_SAMPLE_EDGE

Until now, GSPI_DATA_SAMPLE_EDGE was enabled as soon as the user requested
> 40Mhz (even if the actual frequency was in fact 40Mhz). However, at 40MHz
and at 80MHz, use of GSPI_DATA_SAMPLE_EDGE generated read errors on the
last bit of the transaction:

    Buffer contents are different:
     [...],0xaa,0xaa,0xaa,0xaa,
    vs:
     [...],0xaa,0xaa,0xaa,0xab,

I have not found any case where GSPI_DATA_SAMPLE_EDGE is useful, so this
patch just remove this parameter.

Signed-off-by: Jérôme Pouiller <[email protected]>
Upstream-status: pr <zephyrproject-rtos#100762>

Author: jerome-pouiller

drivers/spi/spi_silabs_siwx91x_gspi.c

@@ -25,7 +25,6 @@ LOG_MODULE_REGISTER(spi_siwx91x_gspi, CONFIG_SPI_LOG_LEVEL);
 #include "spi_context.h"
 
 #define GSPI_MAX_BAUDRATE_FOR_DYNAMIC_CLOCK   110000000
-#define GSPI_MAX_BAUDRATE_FOR_POS_EDGE_SAMPLE 40000000
 #define GSPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE 4096
 #define SPI_HIGH_BURST_FREQ_THRESHOLD_HZ      10000000
 
@@ -157,11 +156,6 @@ static int gspi_siwx91x_config(const struct device *dev, const struct spi_config
 		cfg->reg->GSPI_CLK_CONFIG_b.GSPI_CLK_SYNC = 1;
 	}
 
-	/* Configure data sampling edge for high-speed transfers */
-	if (spi_cfg->frequency > GSPI_MAX_BAUDRATE_FOR_POS_EDGE_SAMPLE) {
-		cfg->reg->GSPI_BUS_MODE_b.GSPI_DATA_SAMPLE_EDGE = 1;
-	}
-
 	/* Set the clock divider factor */
 	cfg->reg->GSPI_CLK_DIV = clk_div_factor;