Issues

• Question about workflow using cross compilation

  UoB-HPC/SimEng#452 · Filter by author Scarlet1ssimo opened on Jan 16, 2025
  4

• simeng runs the FP32 SME instruction with an exception

  UoB-HPC/SimEng#450 · Filter by author zhukang16 opened on Jan 12, 2025
  1

• Broken A64FX port allocator

  bug
  UoB-HPC/SimEng#448 · Filter by author FinnWilkinson opened on Dec 20, 2024

• Update front-end to BP communication timings

  UoB-HPC/SimEng#447 · Filter by author ABenC377 opened on Dec 20, 2024

• Update Dispatch Issue Unit to aid performance

  performance
  UoB-HPC/SimEng#445 · Filter by author FinnWilkinson opened on Dec 16, 2024

• Produce config output file

  UoB-HPC/SimEng#444 · Filter by author ABenC377 opened on Dec 12, 2024

• Issue with ldrsb Instruction Exception

  UoB-HPC/SimEng#440 · Filter by author memory-paper opened on Nov 19, 2024
  4

  

• Fix all the CMake warnings

  UoB-HPC/SimEng#432 · Filter by author tom91136 opened on Oct 2, 2024
  

• Compilation of SimEng fails on Manjaro Linux with GCC 14.2.1

  UoB-HPC/SimEng#426 · Filter by author jandrovins opened on Sep 2, 2024
  4

• Update core model diagram

  UoB-HPC/SimEng#424 · Filter by author ABenC377 opened on Aug 30, 2024
  

• Gtest already imported with external LLVM

  bugbuildtests
  UoB-HPC/SimEng#423 · Filter by author JosephMoore25 opened on Aug 29, 2024
  1

• Fix up random buffer value generation.

  UoB-HPC/SimEng#413 · Filter by author tom91136 opened on May 24, 2024

• Set errno for simulated program

  UoB-HPC/SimEng#410 · Filter by author dANW34V3R opened on Apr 19, 2024
  2

• Integrate BP update with in-order core

  enhancement
  UoB-HPC/SimEng#407 · Filter by author ABenC377 opened on Mar 11, 2024
  

• Regression Test issue when building SimEng : Unit_test SegFault

  UoB-HPC/SimEng#405 · Filter by author elfmath opened on Mar 11, 2024
  1

• Regression Test issue when building SimEng : "fcvtzu" ARM instruction

  UoB-HPC/SimEng#404 · Filter by author elfmath opened on Mar 11, 2024
  1

• Regression Test issue when building SimEng : getrandom syscall

  UoB-HPC/SimEng#403 · Filter by author elfmath opened on Mar 11, 2024
  3

• More registers required to rename all micro-ops than possible causes stalling

  0.9.7bug
  UoB-HPC/SimEng#400 · Filter by author JosephMoore25 opened on Feb 23, 2024

• More micro-operations than ROB size causes stalling and a mem leak

  0.9.7bug
  UoB-HPC/SimEng#399 · Filter by author JosephMoore25 opened on Feb 23, 2024

• Boolean Config Parameter Output

  UoB-HPC/SimEng#398 · Filter by author dANW34V3R opened on Feb 21, 2024

• Fetch Unit Parameterisation

  UoB-HPC/SimEng#397 · Filter by author dANW34V3R opened on Feb 20, 2024
  1

• Handle case of not enough physical registers to rename micro-operations

  0.9.7bug
  UoB-HPC/SimEng#384 · Filter by author JosephMoore25 opened on Feb 5, 2024
  

• [AArch64] Create helper functions for Load and Store instruction execution logic

  code consistencyenhancement
  UoB-HPC/SimEng#378 · Filter by author FinnWilkinson opened on Feb 2, 2024

• Config Docs Range and Core Type Clarifications

  docsenhancement
  UoB-HPC/SimEng#376 · Filter by author dANW34V3R opened on Jan 26, 2024

• Zero register destination operands in multi-destination register AArch64 instructions

  bug
  UoB-HPC/SimEng#375 · Filter by author jj16791 opened on Jan 26, 2024