Reverted workaround from 6aedc46.

Author: Paebbels

.github/workflows/Pipeline.yml

@@ -18,7 +18,7 @@ jobs:
       matrix:
         include:
           - { simulator: 'nvc',  backend: '',      version: 'latest', can-fail: false }
-          - { simulator: 'ghdl', backend: 'mcode', version: 'latest', can-fail: false }
+#          - { simulator: 'ghdl', backend: 'mcode', version: 'latest', can-fail: false }
           - { simulator: 'ghdl', backend: 'llvm',  version: 'latest', can-fail: false }
     with:
       simulator:    ${{ matrix.simulator }}

.github/workflows/Simulate.yml

@@ -307,9 +307,11 @@ jobs:
           }
 
           if {$::osvvm::ToolName eq "GHDL"} {
+            SetExtendedAnalyzeOptions  {-frelaxed -Wno-specs -Wno-elaboration}
             SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
           }
           if {$::osvvm::ToolName eq "NVC"} {
+            SetExtendedAnalyzeOptions {--relaxed}
           }
 
           build ../../tb/RunAllTests.pro

regression.tcl

@@ -31,7 +31,7 @@ source ../lib/OSVVM-Scripts/StartUp.tcl
 build ../lib/OsvvmLibraries.pro
 
 if {$::osvvm::ToolName eq "GHDL"} {
-    SetExtendedAnalyzeOptions {-frelaxed -Wno-specs -Wno-elaboration}
+    SetExtendedAnalyzeOptions  {-frelaxed -Wno-specs -Wno-elaboration}
     SetExtendedSimulateOptions {-frelaxed -Wno-specs -Wno-binding}
 }
 

src/arith/arith_cca.vhdl

@@ -85,7 +85,7 @@ architecture rtl of arith_cca is
       if core <= 0 then
         for j in 0 to i loop
           report integer'image(j)&": ("&integer'image(res(j).base)&", "&integer'image(res(j).core)&", "&integer'image(res(j).done)&")" severity note;
-        end loop;  -- j
+        end loop j;
         return  res(0 to i);
       end if;
       base := base + 2*core;

src/arith/xilinx/arith_cca_xilinx.vhdl

@@ -84,7 +84,7 @@ architecture rtl of arith_cca is
       if core <= 0 then
         for j in 0 to i loop
           report integer'image(j)&": ("&integer'image(res(j).base)&", "&integer'image(res(j).core)&", "&integer'image(res(j).done)&")" severity note;
-        end loop;  -- j
+        end loop j;
         return  res(0 to i);
       end if;
       base := base + 2*core;

src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Subordinate.vhdl

@@ -64,10 +64,7 @@ begin
 
 	AXI4Lite_S2M.ARReady <= not ARFull_i;
 
-	-- WORKAROUND:
-	--  Tool: NVC 1.15.x
-	--  NVC doesn't support inference of others through unconstrained port of type record.
-	AXI4Lite_S2M.RData(AXI4Lite_S2M.RData'range)   <= (others => '0');
+	AXI4Lite_S2M.RData   <= (others => '0');
 	AXI4Lite_S2M.RResp   <= RESPONSE_CODE;
 
 	fifo_aw: fifo_cc_got

src/bus/axi4/AXI4_Termination_Subordinate.vhdl

@@ -63,23 +63,14 @@ begin
 
 	AXI4_S2M.BValid  <= fifo_aw_valid and fifo_w_valid;
 	AXI4_S2M.BResp   <= RESPONSE_CODE;
-	-- WORKAROUND:
-	--  Tool: NVC 1.15.x
-	--  NVC doesn't support inference of others through unconstrained port of type record.
-	AXI4_S2M.BUser(AXI4_S2M.BUser'range)   <= (others => '0');
+	AXI4_S2M.BUser   <= (others => '0');
 
 	AXI4_S2M.ARReady <= not ARFull_i;
 
-	-- WORKAROUND:
-	--  Tool: NVC 1.15.x
-	--  NVC doesn't support inference of others through unconstrained port of type record.
-	AXI4_S2M.RData(AXI4_S2M.RData'range)   <= (others => '0');
+	AXI4_S2M.RData   <= (others => '0');
 	AXI4_S2M.RResp   <= RESPONSE_CODE;
 	AXI4_S2M.RLast   <= '1';
-	-- WORKAROUND:
-	--  Tool: NVC 1.15.x
-	--  NVC doesn't support inference of others through unconstrained port of type record.
-	AXI4_S2M.RUser(AXI4_S2M.RUser'range)   <= (others => '0');
+	AXI4_S2M.RUser   <= (others => '0');
 
 	fifo_aw: fifo_cc_got
 	generic map(

src/bus/axi4/AXI4_to_AXI4Lite.vhdl

@@ -74,7 +74,6 @@ begin
 	Out_M2S.ARProt      <= In_M2S.ARProt ;
 	Out_M2S.RReady      <= In_M2S.RReady ;
 
-
 	In_S2M.AWReady     <= Out_S2M.AWReady and not Response_B_fifo_ful;
 	In_S2M.WReady      <= Out_S2M.WReady ;
 	In_S2M.BValid      <= Out_S2M.BValid ;
@@ -84,11 +83,9 @@ begin
 	In_S2M.RData       <= Out_S2M.RData;
 	In_S2M.RResp       <= Out_S2M.RResp  ;
 	In_S2M.RLast       <= '1';
-	-- WORKAROUND:
-	--  Tool: NVC 1.15.x
-	--  NVC doesn't support inference of others through unconstrained port of type record.
-	In_S2M.BUser(In_S2M.BUser'range) <= (others => '0');
-	In_S2M.RUser(In_S2M.RUser'range) <= (others => '0');
+
+	In_S2M.BUser       <= (others => '0');
+	In_S2M.RUser       <= (others => '0');
 
 	Response_R_fifo : entity work.fifo_shift
 	generic map(

tb/arith/div/arith_div_Simple.vhdl

@@ -100,8 +100,8 @@ begin
       WaitForClock(Clock);
       wait for 1 ns;
       Start <= '0';
-      A     <= (A'range => '-');  -- (others => '-');  WORKAROUND: NVC 1.18.2 Linux
-      D     <= (D'range => '-');  -- (others => '-');
+      A     <= (others => '-');
+      D     <= (others => '-');
       done  := (others => false);
 
       loop
@@ -136,8 +136,8 @@ begin
 
   begin
     Start <= '0';
-		A     <= (A'range => '-');  -- (others => '-');  WORKAROUND: NVC 1.18.2 Linux
-		D     <= (D'range => '-');  -- (others => '-');
+		A     <= (others => '-');
+		D     <= (others => '-');
 
     -- Initialize Random
     Random.InitSeed(Random'instance_name);