implement isnormal function (microsoft#7720)

Add an isnormal function to HLSL with 16 bit and 32 bit float overloads.

Targeting DirectX:
The 32 bit overload uses the IsNormal DXIL Op
In SM6.8 and earlier the 16 bit overload is emulated using LLVM IR
In SM6.9 and later the 16 bit overload uses the IsNormal DXIL Op
Adds unit tests showing the correct IR/DXIL Op is generated for each
float size and SM.

Targeting SPIRV:
OpIsNormal requires the kernel capability, so it cannot be used;
therefore, the isnormal op is emulated.
IsNormal = !(Nan || Inf || Zero || Subnormal)
In the bit pattern of a 16 bit or 32 bit float; a normal number
corresponds to one whose exponent bits are neither all zeros nor all
ones. The emulation code checks that the exponent bits are neither all
zeroes nor all ones.
Adds unit tests showing isnormal is emulated.

Closes microsoft#7648

Author: spall

docs/SPIR-V.rst

@@ -2477,6 +2477,8 @@ extended instruction mapping, so they are handled with additional steps:
 - ``isfinite`` : Determines if the specified value is finite. Since ``OpIsFinite``
   requires the ``Kernel`` capability, translation is done using ``OpIsNan`` and
   ``OpIsInf``.  A given value is finite iff it is not NaN and not infinite.
+- ``isnormal`` : Determines if the specified value is normal (not zero, INF, NAN or subnormal).
+  Since ``OpIsNormal`` requires the ``Kernel`` capability, the operation is emulated.
 - ``clip``: Discards the current pixel if the specified value is less than zero.
   Uses conditional control flow as well as SPIR-V ``OpKill``.
 - ``rcp``: Calculates a fast, approximate, per-component reciprocal.

include/dxc/HlslIntrinsicOp.h

@@ -164,6 +164,7 @@ enum class IntrinsicOp {
   IOP_isfinite = 152,
   IOP_isinf = 153,
   IOP_isnan = 154,
+  IOP_isnormal = 394,
   IOP_ldexp = 155,
   IOP_length = 156,
   IOP_lerp = 157,
@@ -400,7 +401,7 @@ enum class IntrinsicOp {
   IOP_usign = 355,
   MOP_InterlockedUMax = 356,
   MOP_InterlockedUMin = 357,
-  Num_Intrinsics = 394,
+  Num_Intrinsics = 395,
 };
 inline bool HasUnsignedIntrinsicOpcode(IntrinsicOp opcode) {
   switch (opcode) {

lib/HLSL/DxilPreparePasses.cpp

@@ -694,6 +694,26 @@ class DxilFinalizeModule : public ModulePass {
     CI->eraseFromParent();
   }
 
+  // Check if exponent bits are neither all 0s nor all 1s
+  static void emulateIsNormal(Module &M, CallInst *CI) {
+    IRBuilder<> Builder(CI);
+    Value *Val = CI->getOperand(1);
+    DXASSERT(Val->getType()->isHalfTy(),
+             "Only emulates Half overload of IsNormal");
+    Type *IType = Type::getInt16Ty(M.getContext());
+
+    Constant *ExpBitMask = ConstantInt::get(IType, 0x7c00);
+    Constant *Zero = ConstantInt::get(IType, 0);
+
+    Value *IVal = Builder.CreateBitCast(Val, IType);
+    Value *Exp = Builder.CreateAnd(IVal, ExpBitMask);
+    Value *NotAllZeroes = Builder.CreateICmpNE(Exp, Zero);
+    Value *NotAllOnes = Builder.CreateICmpNE(Exp, ExpBitMask);
+    Value *B1 = Builder.CreateAnd(NotAllZeroes, NotAllOnes);
+    CI->replaceAllUsesWith(B1);
+    CI->eraseFromParent();
+  }
+
   // Emulate IsSpecialFloat for Half pre sm6.9
   static void emulateIsSpecialFloat(Module &M, hlsl::OP *hlslOP) {
     // Finds the OpCodeClass that IsInf belongs to, IsSpecialFloat
@@ -719,6 +739,9 @@ class DxilFinalizeModule : public ModulePass {
         case (uint64_t)DXIL::OpCode::IsFinite:
           emulateIsFinite(M, CI);
           continue;
+        case (uint64_t)DXIL::OpCode::IsNormal:
+          emulateIsNormal(M, CI);
+          continue;
         default:
           continue;
         }

lib/HLSL/HLOperationLower.cpp

@@ -7450,6 +7450,7 @@ IntrinsicLower gLowerTable[] = {
      TranslateOuterProductAccumulate, DXIL::OpCode::OuterProductAccumulate},
     {IntrinsicOp::IOP___builtin_VectorAccumulate, TranslateVectorAccumulate,
      DXIL::OpCode::VectorAccumulate},
+    {IntrinsicOp::IOP_isnormal, TrivialIsSpecialFloat, DXIL::OpCode::IsNormal},
 };
 } // namespace
 static_assert(

tools/clang/include/clang/SPIRV/AstTypeProbe.h

@@ -313,6 +313,9 @@ bool isSintOrVecOfSintType(QualType type);
 /// integer type.
 bool isUintOrVecOfUintType(QualType type);
 
+/// Returns true if the given type is a half or vector of half type.
+bool isHalfOrVecOfHalfType(QualType type);
+
 /// Returns true if the given type is a float or vector of float type.
 bool isFloatOrVecOfFloatType(QualType type);
 

tools/clang/lib/SPIRV/AstTypeProbe.cpp

@@ -1280,6 +1280,13 @@ bool isUintOrVecOfUintType(QualType type) {
          elemType->isUnsignedIntegerType();
 }
 
+/// Returns true if the given type is a half or vector of half type.
+bool isHalfOrVecOfHalfType(QualType type) {
+  QualType elemType = {};
+  return (isScalarType(type, &elemType) || isVectorType(type, &elemType)) &&
+         elemType->isHalfType();
+}
+
 /// Returns true if the given type is a float or vector of float type.
 bool isFloatOrVecOfFloatType(QualType type) {
   QualType elemType = {};

tools/clang/lib/SPIRV/SpirvEmitter.cpp

@@ -9658,6 +9658,9 @@ SpirvEmitter::processIntrinsicCallExpr(const CallExpr *callExpr) {
   case hlsl::IntrinsicOp::IOP_isfinite:
     retVal = processIntrinsicIsFinite(callExpr);
     break;
+  case hlsl::IntrinsicOp::IOP_isnormal:
+    retVal = processIntrinsicIsNormal(callExpr);
+    break;
   case hlsl::IntrinsicOp::IOP_EvaluateAttributeCentroid:
   case hlsl::IntrinsicOp::IOP_EvaluateAttributeAtSample:
   case hlsl::IntrinsicOp::IOP_EvaluateAttributeSnapped: {
@@ -12334,6 +12337,73 @@ SpirvEmitter::processIntrinsicIsFinite(const CallExpr *callExpr) {
   return actOnEachVec(/* index= */ 0, arg->getType(), returnType, argId);
 }
 
+SpirvInstruction *
+SpirvEmitter::processIntrinsicIsNormal(const CallExpr *callExpr) {
+  // Since OpIsNormal needs the Kernel capability, translation is instead done
+  // IsNormal = !(zero || NaN || Inf || Subnormal)
+  // Check that the exponent is neither all 0s nor all 1s
+  const auto loc = callExpr->getExprLoc();
+  const auto range = callExpr->getSourceRange();
+  const QualType returnType = callExpr->getType();
+  const Expr *arg = callExpr->getArg(0);
+  auto *argId = doExpr(arg);
+
+  const auto actOnEachVec = [this, loc, range](
+                                uint32_t /*index*/, QualType inType,
+                                QualType outType, SpirvInstruction *curRow) {
+    QualType intTy;
+    SpirvConstant *expMask;
+    SpirvConstant *zero;
+    if (isHalfOrVecOfHalfType(inType)) {
+      intTy = astContext.UnsignedShortTy;
+      expMask = spvBuilder.getConstantInt(intTy, llvm::APInt(16, 0x7c00));
+      zero = spvBuilder.getConstantInt(intTy, llvm::APInt(16, 0));
+    } else {
+      assert(isFloatOrVecOfFloatType(inType));
+      intTy = astContext.UnsignedIntTy;
+      expMask = spvBuilder.getConstantInt(intTy, llvm::APInt(32, 0x7F800000));
+      zero = spvBuilder.getConstantInt(intTy, llvm::APInt(32, 0));
+    }
+
+    QualType boolTy = astContext.BoolTy;
+    uint32_t vecSize;
+    if (isVectorType(inType, nullptr, &vecSize)) {
+      intTy = astContext.getExtVectorType(intTy, vecSize);
+      boolTy = astContext.getExtVectorType(boolTy, vecSize);
+      expMask = spvBuilder.getConstantComposite(
+          intTy, llvm::SmallVector<SpirvConstant *, 4>(vecSize, expMask));
+      zero = spvBuilder.getConstantComposite(
+          intTy, llvm::SmallVector<SpirvConstant *, 4>(vecSize, zero));
+    }
+
+    auto *bitCast =
+        spvBuilder.createUnaryOp(spv::Op::OpBitcast, intTy, curRow, loc);
+    bitCast->setLayoutRule(SpirvLayoutRule::Void);
+    auto *masked = spvBuilder.createBinaryOp(spv::Op::OpBitwiseAnd, intTy,
+                                             bitCast, expMask, loc, range);
+    masked->setLayoutRule(SpirvLayoutRule::Void);
+    auto *notZero = spvBuilder.createBinaryOp(spv::Op::OpINotEqual, boolTy,
+                                              masked, zero, loc, range);
+    notZero->setLayoutRule(SpirvLayoutRule::Void);
+    auto *notOnes = spvBuilder.createBinaryOp(spv::Op::OpINotEqual, boolTy,
+                                              masked, expMask, loc, range);
+    notOnes->setLayoutRule(SpirvLayoutRule::Void);
+    auto *isNormal = spvBuilder.createBinaryOp(spv::Op::OpLogicalAnd, boolTy,
+                                               notZero, notOnes, loc, range);
+    isNormal->setLayoutRule(SpirvLayoutRule::Void);
+    return isNormal;
+  };
+
+  // If the instruction does not operate on matrices, we can perform the
+  // instruction on each vector of the matrix.
+  if (isMxNMatrix(arg->getType())) {
+    assert(isMxNMatrix(returnType));
+    return processEachVectorInMatrix(arg, returnType, argId, actOnEachVec, loc,
+                                     range);
+  }
+  return actOnEachVec(/* index= */ 0, arg->getType(), returnType, argId);
+}
+
 SpirvInstruction *
 SpirvEmitter::processIntrinsicSinCos(const CallExpr *callExpr) {
   // Since there is no sincos equivalent in SPIR-V, we need to perform Sin

tools/clang/lib/SPIRV/SpirvEmitter.h

@@ -639,6 +639,9 @@ class SpirvEmitter : public ASTConsumer {
   /// Processes the 'isFinite' intrinsic function.
   SpirvInstruction *processIntrinsicIsFinite(const CallExpr *);
 
+  /// Processes the 'isNormal' intrinsic function.
+  SpirvInstruction *processIntrinsicIsNormal(const CallExpr *);
+
   /// Processes the 'rcp' intrinsic function.
   SpirvInstruction *processIntrinsicRcp(const CallExpr *);
 

tools/clang/test/CodeGenDXIL/hlsl/intrinsics/IsSpecialFloat6.8.hlsl

@@ -35,3 +35,38 @@ export bool test_isnan(half h) {
 export bool test_isfinite(half h) {
   return isfinite(h);
 }
+
+// CHECK-LABEL: test_isnormal
+// CHECK: [[V1:%.*]] = bitcast half {{.*}} to i16
+// CHECK: [[V2:%.*]] = and i16 [[V1]], 31744
+// CHECK: [[V3:%.*]] = icmp ne i16 [[V2]], 0
+// CHECK: [[V4:%.*]] = icmp ne i16 [[V2]], 31744
+// CHECK: [[V5:%.*]] = and i1 [[V3]], [[V4]]
+// CHECK: ret i1 [[V5]]
+export bool test_isnormal(half h) {
+  return isnormal(h);
+}
+
+// CHECK-LABEL: test_isinf32
+// CHECK: call i1 @dx.op.isSpecialFloat.f32(i32 9, float
+export bool test_isinf32(float f) {
+  return isinf(f);
+}
+
+// CHECK-LABEL: test_isnan32
+// CHECK: call i1 @dx.op.isSpecialFloat.f32(i32 8, float
+export bool test_isnan32(float f) {
+  return isnan(f);
+}
+
+// CHECK-LABEL: test_isfinite32
+// CHECK: call i1 @dx.op.isSpecialFloat.f32(i32 10, float
+export bool test_isfinite32(float f) {
+  return isfinite(f);
+}
+
+// CHECK-LABEL: test_isnormal32
+// CHECK: call i1 @dx.op.isSpecialFloat.f32(i32 11, float
+export bool test_isnormal32(float f) {
+  return isnormal(f);
+}