@@ -134,7 +134,7 @@ static inline void spi_putreg8(struct kinetis_spidev_s *priv,
134134 uint8_t offset , uint8_t value );
135135static inline uint16_t spi_readword (struct kinetis_spidev_s * priv );
136136static inline void spi_writeword (struct kinetis_spidev_s * priv ,
137- uint16_t word );
137+ uint16_t word , bool first_word );
138138
139139static inline void spi_run (struct kinetis_spidev_s * priv ,
140140 bool enable );
@@ -559,27 +559,51 @@ static inline void spi_write_control(struct kinetis_spidev_s *priv,
559559 * Name: spi_writeword
560560 *
561561 * Description:
562- * Write one 16 bit word to SPI TX FIFO
562+ * Write one word to SPI TX FIFO or single-entry buffer.
563+ * In non-FIFO mode, performs 32-bit write including control bits.
564+ * In FIFO-enabled mode, writes only the data (control handled separately).
563565 *
564566 * Input Parameters:
565567 * priv - Device-specific state data
566568 * word - word to send
569+ * first_word - Flag to set control in case of FIFO disabled
567570 *
568571 * Returned Value:
569572 * None
570573 *
571574 ****************************************************************************/
572575
573576static inline void spi_writeword (struct kinetis_spidev_s * priv ,
574- uint16_t word )
577+ uint16_t word , bool first_word )
575578{
579+ uint32_t mcr = spi_getreg (priv , KINETIS_SPI_MCR_OFFSET );
580+ uint32_t pushr_val ;
581+
576582 /* Wait until there is space in the fifo */
577583
578584 spi_wait_status (priv , SPI_SR_TFFF );
579585
580- /* Write the data to transmitted to the SPI Data Register */
586+ if (mcr & SPI_MCR_DIS_TXF )
587+ {
588+ /* FIFO disabled: 32-bit write including control + data */
589+
590+ pushr_val = SPI_PUSHR_TXDATA (word );
591+
592+ if (first_word )
593+ {
594+ /* Set Control word */
595+
596+ pushr_val |= SPI_PUSHR_CTAS_CTAR0 | SPI_PUSHR_CTCNT ;
597+ }
598+
599+ spi_putreg (priv , KINETIS_SPI_PUSHR_OFFSET , pushr_val );
600+ }
601+ else
602+ {
603+ /* FIFO enabled: write only data; control handled separately */
581604
582- spi_putreg16 (priv , KINETIS_SPI_PUSHR_OFFSET , SPI_PUSHR_TXDATA (word ));
605+ spi_putreg16 (priv , KINETIS_SPI_PUSHR_OFFSET , SPI_PUSHR_TXDATA (word ));
606+ }
583607}
584608
585609/****************************************************************************
@@ -964,16 +988,27 @@ static uint16_t spi_send_data(struct kinetis_spidev_s *priv, uint16_t wd,
964988 bool last )
965989{
966990 uint16_t ret ;
991+ uint32_t mcr = spi_getreg (priv , KINETIS_SPI_MCR_OFFSET );
992+ bool first_word = false;
967993
968- /* On first write set control word and start transfer */
994+ /* Start module and write control if FIFO enabled on first transfer */
969995
970- if (0 == (spi_getreg (priv , KINETIS_SPI_SR_OFFSET ) & SPI_SR_TXRXS ))
996+ if ((spi_getreg (priv , KINETIS_SPI_SR_OFFSET ) & SPI_SR_TXRXS ) == 0 )
971997 {
972998 spi_run (priv , true);
973- spi_write_control (priv , SPI_PUSHR_CTAS_CTAR0 | SPI_PUSHR_CTCNT );
999+ first_word = true;
1000+
1001+ if ((mcr & SPI_MCR_DIS_TXF ) == 0 )
1002+ {
1003+ /* FIFO enabled: safe to write control separately */
1004+
1005+ spi_write_control (priv , SPI_PUSHR_CTAS_CTAR0 | SPI_PUSHR_CTCNT );
1006+ }
1007+
1008+ /* Non-FIFO mode: first_word flag used in spi_writeword() */
9741009 }
9751010
976- spi_writeword (priv , wd );
1011+ spi_writeword (priv , wd , first_word );
9771012 ret = spi_readword (priv );
9781013
9791014 if (!last )
@@ -1037,15 +1072,14 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
10371072 *
10381073 ****************************************************************************/
10391074
1040- #if !defined(CONFIG_STM32_SPI_DMA ) || defined(CONFIG_STM32_SPI_DMATHRESHOLD )
1041- # if !defined(CONFIG_KINETIS_SPI_DMA )
1075+ #if !defined(CONFIG_KINETIS_SPI_DMA )
10421076static void spi_exchange (struct spi_dev_s * dev , const void * txbuffer ,
10431077 void * rxbuffer , size_t nwords )
1044- # else
1078+ #else
10451079static void spi_exchange_nodma (struct spi_dev_s * dev ,
10461080 const void * txbuffer ,
10471081 void * rxbuffer , size_t nwords )
1048- # endif
1082+ #endif
10491083{
10501084 struct kinetis_spidev_s * priv = (struct kinetis_spidev_s * )dev ;
10511085 uint8_t * brxptr = (uint8_t * )rxbuffer ;
@@ -1117,7 +1151,6 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
11171151 }
11181152 }
11191153}
1120- #endif /* !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_SPI_DMATHRESHOLD) */
11211154
11221155/****************************************************************************
11231156 * Name: spi_exchange (with DMA capability)
@@ -1620,13 +1653,13 @@ struct spi_dev_s *kinetis_spibus_initialize(int port)
16201653 * Peripheral Chip Select Strobe - Peripheral Chip Select[5] signal
16211654 * Receive FIFO Overflow Overwrite - Ignore incoming
16221655 * Chip Select x Inactive State - High
1623- * Doze - Disabled
1656+ * Doze - Disabled
16241657 * Module Disable - Enables the module clocks.
16251658 * Disable Transmit FIFO - yes
16261659 * Disable Receive FIFO - yes
16271660 * Clear TX FIFO - No
16281661 * Clear RX FIFO - No
1629- * Sample Point - 0 clocks between edge and sample
1662+ * Sample Point - 0 clocks between edge and sample
16301663 *
16311664 */
16321665
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