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freedom-k64f map and configure spi 0 driver #17152
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trns1997
commented
Oct 2, 2025
2 tasks
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@trns1997 please fix the coding style issues and add message log in the commits explaining why this patch is necessary, basically to explain which problem are you fixing. Is it necessary to communicate with some SPI device? |
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xiaoxiang781216
previously approved these changes
Nov 10, 2025
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@trns1997 please fix these errors: |
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xiaoxiang781216
previously approved these changes
Nov 10, 2025
Fix a transfer issue in the Kinetis DSPI driver when operating with transmit and receive FIFOs disabled (`MCR[DIS_TXF]=1`, `MCR[DIS_RXF]=1`). In this mode, the DSPI module behaves as a simple double-buffered SPI interface without TX staging. When FIFOs are disabled, `PUSHR` acts as a single 32-bit command/data register. Partial (16-bit) writes to its upper or lower halves can result in incomplete or corrupted transfers. This patch ensures the full 32-bit packet is prepared and written in a single operation. * Resolves broken SPI transactions with LAN9252 (EasyCAT). * Improves reliability in non-FIFO DSPI configurations. * No impact on DMA or FIFO-enabled modes. Signed-off-by: trns1997 <[email protected]>
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ping @leducp, this should help us complete the kickcat example :) |
xiaoxiang781216
approved these changes
Nov 11, 2025
leducp
approved these changes
Nov 12, 2025
jerpelea
approved these changes
Nov 12, 2025
simbit18
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Nov 12, 2025
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Labels
Arch: arm
Issues related to ARM (32-bit) architecture
Board: arm
Size: M
The size of the change in this PR is medium
Size: S
The size of the change in this PR is small
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Summary
This patch fixes a minor SPI transfer issue in the Kinetis DSPI driver when operating with the transmit and receive FIFOs disabled (
MCR[DIS_TXF]=1,MCR[DIS_RXF]=1).In non-FIFO mode, the DSPI module operates as a simplified double-buffered SPI interface without internal TX staging.
When FIFOs are disabled,
PUSHRacts as a single 32-bit command/data block [PUSHR = [command bits | data bits]]. Partial (16-bit) writes to its upper and lower halves are not guaranteed to combine coherently and can lead to incomplete or corrupted transfers. So the idea is to prepare the 32 bit packet and put with 1 function call instead of doing it in 2 steps, as done when FIFO is enabled.
References:
This change resolves problematic SPI transactions observed with the LAN9252 EtherCAT slave [EasyCAT].
Impact
Testing
Testing was performed on a Kinetis K64F board connected to an EasyCAT (LAN9252-based) EtherCAT slave.