refactor: modify page table

Co-authored-by: 朝倉水希 <[email protected]>

Author: AsakuraMizu

Cargo.lock

@@ -19,6 +19,7 @@ copy-from = ["dep:bitmaps"]
 
 [dependencies]
 axerrno = { version = "0.1", optional = true }
+arrayvec = { version = "0.7", default-features = false }
 bitmaps = { version = "3.2", default-features = false, optional = true }
 log = "0.4"
 memory_addr.workspace = true

page_table_multiarch/Cargo.toml

@@ -66,6 +66,6 @@ let flags = MappingFlags::READ | MappingFlags::WRITE;
 let mut pt = X64PageTable::<PagingHandlerImpl>::try_new().unwrap();
 
 assert!(pt.root_paddr().is_aligned_4k());
-assert!(pt.map(vaddr, paddr, PageSize::Size4K, flags).is_ok());
+assert!(pt.modify().map(vaddr, paddr, PageSize::Size4K, flags).is_ok());
 assert_eq!(pt.query(vaddr), Ok((paddr, flags, PageSize::Size4K)));
 ```

page_table_multiarch/README.md

@@ -5,7 +5,7 @@ use core::arch::asm;
 use memory_addr::VirtAddr;
 use page_table_entry::aarch64::A64PTE;
 
-use crate::{PageTable64, PagingMetaData};
+use crate::{PageTable64, PageTable64Mut, PagingMetaData};
 
 /// Metadata of AArch64 page tables.
 pub struct A64PagingMetaData;
@@ -38,3 +38,5 @@ impl PagingMetaData for A64PagingMetaData {
 
 /// AArch64 VMSAv8-64 translation table.
 pub type A64PageTable<H> = PageTable64<A64PagingMetaData, A64PTE, H>;
+/// Mutable reference to an AArch64 VMSAv8-64 translation table.
+pub type A64PageTableMut<'a, H> = PageTable64Mut<'a, A64PagingMetaData, A64PTE, H>;

page_table_multiarch/src/arch/aarch64.rs

@@ -5,7 +5,7 @@ use core::arch::asm;
 use memory_addr::VirtAddr;
 use page_table_entry::loongarch64::LA64PTE;
 
-use crate::{PageTable64, PagingMetaData};
+use crate::{PageTable64, PageTable64Mut, PagingMetaData};
 
 /// Metadata of LoongArch64 page tables.
 #[derive(Copy, Clone, Debug)]
@@ -86,3 +86,5 @@ impl PagingMetaData for LA64MetaData {
 ///
 /// using page table dir3, dir2, dir1 and pt, ignore dir4
 pub type LA64PageTable<H> = PageTable64<LA64MetaData, LA64PTE, H>;
+/// Mutable reference to a loongarch64 page table.
+pub type LA64PageTableMut<'a, H> = PageTable64Mut<'a, LA64MetaData, LA64PTE, H>;

page_table_multiarch/src/arch/loongarch64.rs

@@ -3,7 +3,7 @@
 use memory_addr::VirtAddr;
 use page_table_entry::riscv::Rv64PTE;
 
-use crate::{PageTable64, PagingMetaData};
+use crate::{PageTable64, PageTable64Mut, PagingMetaData};
 
 /// A virtual address that can be used in RISC-V Sv39 and Sv48 page tables.
 pub trait SvVirtAddr: memory_addr::MemoryAddr + Send + Sync {
@@ -58,6 +58,10 @@ impl<VA: SvVirtAddr> PagingMetaData for Sv48MetaData<VA> {
 
 /// Sv39: Page-Based 39-bit (3 levels) Virtual-Memory System.
 pub type Sv39PageTable<H> = PageTable64<Sv39MetaData<VirtAddr>, Rv64PTE, H>;
+/// Mutable reference to a RISC-V Sv39 page table.
+pub type Sv39PageTableMut<'a, H> = PageTable64Mut<'a, Sv39MetaData<VirtAddr>, Rv64PTE, H>;
 
 /// Sv48: Page-Based 48-bit (4 levels) Virtual-Memory System.
 pub type Sv48PageTable<H> = PageTable64<Sv48MetaData<VirtAddr>, Rv64PTE, H>;
+/// Mutable reference to a RISC-V Sv48 page table.
+pub type Sv48PageTableMut<'a, H> = PageTable64Mut<'a, Sv48MetaData<VirtAddr>, Rv64PTE, H>;

page_table_multiarch/src/arch/riscv.rs

@@ -3,7 +3,7 @@
 use memory_addr::VirtAddr;
 use page_table_entry::x86_64::X64PTE;
 
-use crate::{PageTable64, PagingMetaData};
+use crate::{PageTable64, PageTable64Mut, PagingMetaData};
 
 /// metadata of x86_64 page tables.
 pub struct X64PagingMetaData;
@@ -28,3 +28,5 @@ impl PagingMetaData for X64PagingMetaData {
 
 /// x86_64 page table.
 pub type X64PageTable<H> = PageTable64<X64PagingMetaData, X64PTE, H>;
+/// Mutable reference to an x86_64 page table.
+pub type X64PageTableMut<'a, H> = PageTable64Mut<'a, X64PagingMetaData, X64PTE, H>;