diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst index 6d835c9ce..8fa448588 100644 --- a/doc/02_user/integration.rst +++ b/doc/02_user/integration.rst @@ -163,7 +163,21 @@ Instantiation Template .alert_minor_o (), .alert_major_internal_o (), .alert_major_bus_o (), - .core_sleep_o () + .core_sleep_o (), + + // Lockstep signals + .lockstep_cmp_en_o (), + + // Shadow core data interface outputs + .data_req_shadow_o (), + .data_we_shadow_o (), + .data_be_shadow_o (), + .data_addr_shadow_o (), + .data_wdata_shadow_o (), + + // Shadow core instruction interface outputs + .instr_req_shadow_o (), + .instr_addr_shadow_o () ); Parameters diff --git a/dv/formal/check/top.sv b/dv/formal/check/top.sv index a10d7a4f8..7b87a7e25 100644 --- a/dv/formal/check/top.sv +++ b/dv/formal/check/top.sv @@ -110,7 +110,21 @@ module top import ibex_pkg::*; #( // DFT bypass controls - input logic scan_rst_ni + input logic scan_rst_ni, + + // Lockstep signals + output ibex_mubi_t lockstep_cmp_en_o, + + // Shadow core data interface outputs + output logic data_req_shadow_o, + output logic data_we_shadow_o, + output logic [3:0] data_be_shadow_o, + output logic [31:0] data_addr_shadow_o, + output logic [31:0] data_wdata_shadow_o, + + // Shadow core instruction interface outputs + output logic instr_req_shadow_o, + output logic [31:0] instr_addr_shadow_o ); // Yosys based tools have no inherent understanding of a reset signal (unlike jasper, which has the diff --git a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv index ea0b2e82c..e346b2de6 100644 --- a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv +++ b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv @@ -215,7 +215,18 @@ module ibex_riscv_compliance ( .alert_minor_o ( ), .alert_major_internal_o ( ), .alert_major_bus_o ( ), - .core_sleep_o ( ) + .core_sleep_o ( ), + + .lockstep_cmp_en_o ( ), + + .data_req_shadow_o ( ), + .data_we_shadow_o ( ), + .data_be_shadow_o ( ), + .data_addr_shadow_o ( ), + .data_wdata_shadow_o ( ), + + .instr_req_shadow_o ( ), + .instr_addr_shadow_o ( ) ); // SRAM block for instruction and data storage diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv index b4107f41a..1e86ba57c 100644 --- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv +++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv @@ -168,7 +168,17 @@ module core_ibex_tb_top; .alert_minor_o (dut_if.alert_minor ), .alert_major_internal_o (dut_if.alert_major_internal), .alert_major_bus_o (dut_if.alert_major_bus ), - .core_sleep_o (dut_if.core_sleep ) + .core_sleep_o (dut_if.core_sleep ), + + .lockstep_cmp_en_o ( ), + .data_req_shadow_o ( ), + .data_we_shadow_o ( ), + .data_be_shadow_o ( ), + .data_addr_shadow_o ( ), + .data_wdata_shadow_o ( ), + + .instr_req_shadow_o ( ), + .instr_addr_shadow_o ( ) ); `define IBEX_RF_PATH core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv index 155fbe893..171de0e45 100644 --- a/examples/simple_system/rtl/ibex_simple_system.sv +++ b/examples/simple_system/rtl/ibex_simple_system.sv @@ -268,7 +268,18 @@ module ibex_simple_system ( .alert_minor_o (), .alert_major_internal_o (), .alert_major_bus_o (), - .core_sleep_o () + .core_sleep_o (), + + .lockstep_cmp_en_o (), + + .data_req_shadow_o (), + .data_we_shadow_o (), + .data_be_shadow_o (), + .data_addr_shadow_o (), + .data_wdata_shadow_o (), + + .instr_req_shadow_o (), + .instr_addr_shadow_o () ); // SRAM block for instruction and data storage diff --git a/rtl/ibex_lockstep.sv b/rtl/ibex_lockstep.sv index 61dc450d6..0c544b7af 100644 --- a/rtl/ibex_lockstep.sv +++ b/rtl/ibex_lockstep.sv @@ -113,7 +113,16 @@ module ibex_lockstep import ibex_pkg::*; #( output logic alert_major_bus_o, input ibex_mubi_t core_busy_i, input logic test_en_i, - input logic scan_rst_ni + input logic scan_rst_ni, + + output ibex_mubi_t lockstep_cmp_en_o, + output logic data_req_shadow_o, + output logic data_we_shadow_o, + output logic [3:0] data_be_shadow_o, + output logic [31:0] data_addr_shadow_o, + output logic [31:0] data_wdata_shadow_o, + output logic instr_req_shadow_o, + output logic [31:0] instr_addr_shadow_o ); localparam int unsigned LockstepOffsetW = $clog2(LockstepOffset); @@ -511,4 +520,13 @@ module ibex_lockstep import ibex_pkg::*; #( assign alert_major_bus_o = shadow_alert_major_bus; assign alert_minor_o = shadow_alert_minor; + assign lockstep_cmp_en_o = enable_cmp_q; + + assign data_req_shadow_o = shadow_outputs_d.data_req; + assign data_we_shadow_o = shadow_outputs_d.data_we; + assign data_be_shadow_o = shadow_outputs_d.data_be; + assign data_addr_shadow_o = shadow_outputs_d.data_addr; + assign data_wdata_shadow_o = shadow_outputs_d.data_wdata[31:0]; + assign instr_req_shadow_o = shadow_outputs_d.instr_req; + assign instr_addr_shadow_o = shadow_outputs_d.instr_addr; endmodule diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv index 20a8822d0..9c91f1511 100644 --- a/rtl/ibex_top.sv +++ b/rtl/ibex_top.sv @@ -34,6 +34,8 @@ module ibex_top import ibex_pkg::*; #( parameter bit DbgTriggerEn = 1'b0, parameter int unsigned DbgHwBreakNum = 1, parameter bit SecureIbex = 1'b0, + parameter bit MemECC = SecureIbex, + parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32, parameter bit ICacheScramble = 1'b0, parameter int unsigned ICacheScrNumPrinceRoundsHalf = 2, parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, @@ -162,7 +164,21 @@ module ibex_top import ibex_pkg::*; #( output logic core_sleep_o, // DFT bypass controls - input logic scan_rst_ni + input logic scan_rst_ni, + + // Lockstep signals + output ibex_mubi_t lockstep_cmp_en_o, + + // Shadow core data interface outputs + output logic data_req_shadow_o, + output logic data_we_shadow_o, + output logic [3:0] data_be_shadow_o, + output logic [31:0] data_addr_shadow_o, + output logic [31:0] data_wdata_shadow_o, + + // Shadow core instruction interface outputs + output logic instr_req_shadow_o, + output logic [31:0] instr_addr_shadow_o ); localparam bit Lockstep = SecureIbex; @@ -172,8 +188,6 @@ module ibex_top import ibex_pkg::*; #( localparam bit RegFileWrenCheck = SecureIbex; localparam bit RegFileRdataMuxCheck = SecureIbex; localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32; - localparam bit MemECC = SecureIbex; - localparam int unsigned MemDataWidth = MemECC ? 32 + 7 : 32; // Icache parameters localparam int unsigned BusSizeECC = ICacheECC ? (BUS_SIZE + 7) : BUS_SIZE; localparam int unsigned LineSizeECC = BusSizeECC * IC_LINE_BEATS; @@ -1123,7 +1137,16 @@ module ibex_top import ibex_pkg::*; #( .alert_major_bus_o (lockstep_alert_major_bus_local), .core_busy_i (core_busy_local), .test_en_i (test_en_i), - .scan_rst_ni (scan_rst_ni) + .scan_rst_ni (scan_rst_ni), + + .lockstep_cmp_en_o (lockstep_cmp_en_o), + .data_req_shadow_o (data_req_shadow_o), + .data_we_shadow_o (data_we_shadow_o), + .data_be_shadow_o (data_be_shadow_o), + .data_addr_shadow_o (data_addr_shadow_o), + .data_wdata_shadow_o (data_wdata_shadow_o), + .instr_req_shadow_o (instr_req_shadow_o), + .instr_addr_shadow_o (instr_addr_shadow_o) ); prim_buf u_prim_buf_alert_minor ( @@ -1145,6 +1168,16 @@ module ibex_top import ibex_pkg::*; #( assign lockstep_alert_major_internal = 1'b0; assign lockstep_alert_major_bus = 1'b0; assign lockstep_alert_minor = 1'b0; + + assign lockstep_cmp_en_o = IbexMuBiOff; + assign data_req_shadow_o = 1'b0; + assign data_we_shadow_o = 1'b0; + assign data_be_shadow_o = '0; + assign data_addr_shadow_o = '0; + assign data_wdata_shadow_o = '0; + assign instr_req_shadow_o = 1'b0; + assign instr_addr_shadow_o = '0; + logic unused_scan; assign unused_scan = scan_rst_ni; end diff --git a/rtl/ibex_top_tracing.sv b/rtl/ibex_top_tracing.sv index 66e759763..612660a41 100644 --- a/rtl/ibex_top_tracing.sv +++ b/rtl/ibex_top_tracing.sv @@ -25,6 +25,8 @@ module ibex_top_tracing import ibex_pkg::*; #( parameter bit DbgTriggerEn = 1'b0, parameter int unsigned DbgHwBreakNum = 1, parameter bit SecureIbex = 1'b0, + parameter bit MemECC = SecureIbex, + parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32, parameter bit ICacheScramble = 1'b0, parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, @@ -95,8 +97,21 @@ module ibex_top_tracing import ibex_pkg::*; #( output logic alert_minor_o, output logic alert_major_internal_o, output logic alert_major_bus_o, - output logic core_sleep_o + output logic core_sleep_o, + // Lockstep signals + output ibex_mubi_t lockstep_cmp_en_o, + + // Shadow core data interface outputs + output logic data_req_shadow_o, + output logic data_we_shadow_o, + output logic [3:0] data_be_shadow_o, + output logic [31:0] data_addr_shadow_o, + output logic [31:0] data_wdata_shadow_o, + + // Shadow core instruction interface outputs + output logic instr_req_shadow_o, + output logic [31:0] instr_addr_shadow_o ); // ibex_tracer relies on the signals from the RISC-V Formal Interface @@ -195,6 +210,8 @@ module ibex_top_tracing import ibex_pkg::*; #( .DbgHwBreakNum ( DbgHwBreakNum ), .WritebackStage ( WritebackStage ), .SecureIbex ( SecureIbex ), + .MemECC ( MemECC ), + .MemDataWidth ( MemDataWidth ), .ICacheScramble ( ICacheScramble ), .RndCnstLfsrSeed ( RndCnstLfsrSeed ), .RndCnstLfsrPerm ( RndCnstLfsrPerm ), @@ -294,7 +311,18 @@ module ibex_top_tracing import ibex_pkg::*; #( .alert_minor_o, .alert_major_internal_o, .alert_major_bus_o, - .core_sleep_o + .core_sleep_o, + + .lockstep_cmp_en_o, + + .data_req_shadow_o, + .data_we_shadow_o, + .data_be_shadow_o, + .data_addr_shadow_o, + .data_wdata_shadow_o, + + .instr_req_shadow_o, + .instr_addr_shadow_o ); ibex_tracer