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‎README.md‎

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# hust-cse-crypto-verilog
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华中科技大学网络空间安全学院密码工程学基础2023
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# hust-cse-crypto-verilog
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**华中科技大学网络空间安全学院密码工程学基础2023**
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*powered by mxy*
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------
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*First，用过本课程库的请star一下~*
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四个实验分别在四个文件夹里，请使用iverilog编译，先编译代码本体如`aes.v`，再编译`test bench`如`tb_aes.v`。
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编译工具链推荐使用`vscode`+`iverilog`，具体安装方法请自行搜索(知乎上有)。
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需要烧录在`FPGA`板子上的，请使用`vivado`生成比特流（课程第一节课会讲），同时，仿真占比90%，纯仿真使用`vscode`即可。

‎实验1(UART)/Computation.v‎

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`timescale 1ns / 1ps
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module Computation(
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Clk ,
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Rst ,
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In_enable ,
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Out_done ,
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// FIFO
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In_rcv_dout ,
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Out_rcv_rd_en ,
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Out_snd_din ,
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Out_snd_wr_en
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);
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//---------------------------------------------------------------------------------------
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// Parameter
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//---------------------------------------------------------------------------------------
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parameter TCQ = 1 ;
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//FSM-------------------------------------------------------------------
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parameter STA_IDLE = 4'h0 ;
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parameter STA_READING = 4'h1 ;
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parameter STA_ROUND = 4'h2 ;
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parameter STA_ROUND_DONE = 4'h3 ;
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parameter STA_WRITING = 4'h4 ;
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parameter STA_COMPUTING_DONE = 4'h5 ;
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//---------------------------------------------------------------------------------------
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// Port Define
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//---------------------------------------------------------------------------------------
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input wire Clk ;
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input wire Rst ;
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input wire In_enable ;
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output wire Out_done ;
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// FIFO
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input wire [31:0] In_rcv_dout ;
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output wire Out_rcv_rd_en ;
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output wire [31:0] Out_snd_din ;
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output wire Out_snd_wr_en ;
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//---------------------------------------------------------------------------------------
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// Signals
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//---------------------------------------------------------------------------------------
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reg out_done ;
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reg out_rcv_rd_en ;
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reg [31:0] out_snd_din ;
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reg out_snd_wr_en ;
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reg [31:0] rcv_dout ;
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reg [31:0] tmp ;
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reg [7:0] cnt_round ;
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//---------------------------------------------------------------------------------------
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// Instance
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//---------------------------------------------------------------------------------------
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//CompIla InstCompIla(
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// .clk (Clk ), // input wire clk
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// .probe0 (In_enable ), // input wire [0:0] probe0
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// .probe1 (Out_done ), // input wire [0:0] probe1
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// .probe2 (In_rcv_dout ), // input wire [31:0] probe2
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// .probe3 (Out_rcv_rd_en ), // input wire [0:0] probe3
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// .probe4 (Out_snd_din ), // input wire [31:0] probe4
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// .probe5 (Out_snd_wr_en ), // input wire [0:0] probe5
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// .probe6 (curr_state ), // input wire [7:0] probe6
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// .probe7 (cnt_round ) // input wire [7:0] probe7
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//);
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//---------------------------------------------------------------------------------------
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// Function Codes
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//---------------------------------------------------------------------------------------
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assign Out_done = out_done;
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assign Out_rcv_rd_en = out_rcv_rd_en;
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assign Out_snd_din = out_snd_din;
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assign Out_snd_wr_en = out_snd_wr_en;
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//---------------------------------------------------------------------------------------
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// FSM
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//---------------------------------------------------------------------------------------
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reg [7:0] curr_state ;
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reg [7:0] next_state ;
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//State Tranfer
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always @(posedge Clk) begin
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if(Rst == 1'b1)
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curr_state <= #TCQ STA_IDLE;
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else
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curr_state <= #TCQ next_state;
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end
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//Calculate the next state
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always @( * ) begin
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case(curr_state)
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STA_IDLE : begin
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if(In_enable)
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next_state = STA_READING;
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else
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next_state = STA_IDLE;
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end
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STA_READING : begin
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next_state = STA_ROUND;
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end
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STA_ROUND : begin
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next_state = STA_ROUND_DONE;
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end
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STA_ROUND_DONE : begin
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next_state = STA_WRITING;
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end
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STA_WRITING : begin
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if(cnt_round < 8'd4)
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next_state = STA_READING;
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else if(cnt_round == 8'd4)
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next_state = STA_COMPUTING_DONE;
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end
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STA_COMPUTING_DONE : begin
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next_state = STA_IDLE;
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end
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default : begin
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next_state = STA_IDLE;
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end
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endcase
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end
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//state output
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always @(posedge Clk) begin
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if(Rst == 1'b1) begin
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out_rcv_rd_en <= #TCQ 1'b0;
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out_snd_wr_en <= #TCQ 1'b0;
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out_snd_din <= #TCQ 32'd0;
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rcv_dout <= #TCQ 32'd0;
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out_done <= #TCQ 1'b0;
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cnt_round <= #TCQ 8'd0;
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end
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else case(curr_state)
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STA_IDLE : begin
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out_rcv_rd_en <= #TCQ 1'b0;
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out_snd_wr_en <= #TCQ 1'b0;
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out_snd_din <= #TCQ 32'd0;
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rcv_dout <= #TCQ 32'd0;
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out_done <= #TCQ 1'b0;
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cnt_round <= #TCQ 8'd0;
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end
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STA_READING : begin
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out_snd_wr_en <= #TCQ 1'b0;
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out_snd_din <= #TCQ 32'd0;
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out_rcv_rd_en <= #TCQ 1'b1;
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rcv_dout <= #TCQ In_rcv_dout;
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end
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STA_ROUND : begin
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out_rcv_rd_en <= #TCQ 1'b0;
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tmp <= #TCQ {rcv_dout[7:0], rcv_dout[15:8], rcv_dout[23:16], rcv_dout[31:24]};
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end
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STA_ROUND_DONE : begin
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cnt_round <= #TCQ cnt_round + 8'd1;
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end
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STA_WRITING : begin
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out_snd_wr_en <= #TCQ 1'b1;
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out_snd_din <= #TCQ tmp;
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end
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STA_COMPUTING_DONE : begin
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out_snd_wr_en <= #TCQ 1'b0;
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out_done <= #TCQ 1'b1;
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end
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endcase
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end
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endmodule
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‎实验1(UART)/Top.v‎

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`timescale 1ns / 1ps
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module Top(
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Clk_p ,
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Clk_n ,
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//Rx and Tx
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In_rx ,
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Out_tx
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);
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//---------------------------------------------------------------------------------------
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// Parameter
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//---------------------------------------------------------------------------------------
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parameter TCQ = 1 ;
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//---------------------------------------------------------------------------------------
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// Port Define
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//---------------------------------------------------------------------------------------
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input wire Clk_p ;
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input wire Clk_n ;
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//Rx and Tx
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input wire In_rx ;
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output wire Out_tx ;
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//---------------------------------------------------------------------------------------
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// Signals
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//---------------------------------------------------------------------------------------
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//ClkWid
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wire clk200m ;
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wire clk100m ;
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wire clk50m ;
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wire locked ;
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//RcvFifo
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wire [7:0] rcv_din ;
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wire rcv_wr_en ;
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wire rcv_full ;
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wire [5:0] rcv_wr_data_count ;
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wire [31:0] rcv_dout ;
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wire rcv_rd_en ;
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wire rcv_empty ;
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wire [3:0] rcv_rd_data_count ;
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//SndFifo
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wire [31:0] snd_din ;
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wire snd_wr_en ;
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wire snd_full ;
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wire [3:0] snd_wr_data_count ;
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wire [7:0] snd_dout ;
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wire snd_rd_en ;
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wire snd_empty ;
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wire [5:0] snd_rd_data_count ;
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//Computation
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wire comp_enable ;
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wire comp_done ;
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//---------------------------------------------------------------------------------------
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// Instance
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//---------------------------------------------------------------------------------------
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IBUFGDS InstClkTrans
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(
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.O(clk200m),
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.I(Clk_p),
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.IB(Clk_n)
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);
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ClkWiz InstClkWiz(
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.clk_out100m (clk100m ), // output clk_out100m
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.clk_out50m (clk50m ), // output clk_out50m
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.clk_in200m (clk200m ), // input clk_in100m
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.locked (locked )
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);
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Uart InstUart(
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.Clk (clk100m ),
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.Rst (!locked ),
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//Rx and Tx
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.In_rx (In_rx ),
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.Out_tx (Out_tx ),
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//FIFO
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.In_rcv_wr_data_count (rcv_wr_data_count ),
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.In_rcv_full (rcv_full ),
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.Out_rcv_wr_en (rcv_wr_en ),
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.Out_rcv_din (rcv_din ),
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.In_snd_rd_data_count (snd_rd_data_count ),
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.In_snd_empty (snd_empty ),
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.Out_snd_rd_en (snd_rd_en ),
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.In_snd_dout (snd_dout ),
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//Computation
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.In_comp_done (comp_done ),
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.Out_comp_enable (comp_enable )
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);
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RcvFifo InstRcvFifo(
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.rst (!locked ), // input wire rst
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.wr_clk (clk100m ), // input wire wr_clk
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.rd_clk (clk50m ), // input wire rd_clk
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.din (rcv_din ), // input wire [7 : 0] din
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.wr_en (rcv_wr_en ), // input wire wr_en
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.rd_en (rcv_rd_en ), // input wire rd_en
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.dout (rcv_dout ), // output wire [31 : 0] dout
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.full (rcv_full ), // output wire full
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.empty (rcv_empty ), // output wire empty
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.rd_data_count (rcv_rd_data_count ), // output wire [3 : 0] rd_data_count
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.wr_data_count (rcv_wr_data_count ) // output wire [5 : 0] wr_data_count
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);
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SndFifo InstSndFifo(
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.rst (!locked ), // input wire rst
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.wr_clk (clk50m ), // input wire wr_clk
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.rd_clk (clk100m ), // input wire rd_clk
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.din (snd_din ), // input wire [31 : 0] din
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.wr_en (snd_wr_en ), // input wire wr_en
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.rd_en (snd_rd_en ), // input wire rd_en
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.dout (snd_dout ), // output wire [7 : 0] dout
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.full (snd_full ), // output wire full
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.empty (snd_empty ), // output wire empty
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.rd_data_count (snd_rd_data_count ), // output wire [5 : 0] rd_data_count
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.wr_data_count (snd_wr_data_count ) // output wire [3 : 0] wr_data_count
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);
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Computation InstComputation(
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.Clk (clk50m ),
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.Rst (!locked ),
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.In_enable (comp_enable ),
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.Out_done (comp_done ),
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//FIFO
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.In_rcv_dout (rcv_dout ),
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.Out_rcv_rd_en (rcv_rd_en ),
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.Out_snd_din (snd_din ),
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.Out_snd_wr_en (snd_wr_en )
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);
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//ILA
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TopIla InstTopIla(
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.clk (clk100m ), // input wire clk
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.probe0 (comp_enable ), // input wire [0:0] probe0
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.probe1 (comp_done ), // input wire [0:0] probe1
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.probe2 (rcv_dout ), // input wire [31:0] probe2
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.probe3 (rcv_rd_en ), // input wire [0:0] probe3
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.probe4 (snd_din ), // input wire [31:0] probe4
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.probe5 (snd_wr_en ), // input wire [0:0] probe5
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.probe6 (snd_empty ), // input wire [0:0] probe6
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.probe7 (snd_rd_data_count ) // input wire [5:0] probe7
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//.probe8 ( ), // input wire [0:0] probe8
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//.probe9 ( ), // input wire [0:0] probe9
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//.probe10 ( ), // input wire [0:0] probe10
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//.probe11 ( ), // input wire [0:0] probe11
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//.probe12 ( ), // input wire [0:0] probe12
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//.probe13 ( ), // input wire [0:0] probe13
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//.probe14 ( ), // input wire [0:0] probe14
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//.probe15 ( ) // input wire [0:0] probe15
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);
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//---------------------------------------------------------------------------------------
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// Function Codes
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// FSM
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//---------------------------------------------------------------------------------------
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endmodule
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