-
Notifications
You must be signed in to change notification settings - Fork 154
Home
Welcome to the mor1kx wiki!
The mor1kx is an OpenRISC 1000 (or1k) compliant CPU implementation which is written in synthesisable Verilog.
There's more documentation in AsciiDoc format in the doc/ path.
See this guide on setting up and using a simulation environment for the mor1kx core.
Out of interest, here is how much code there is as of commit 3e1de595ea8adcdd75edfb7cc748eadddafee168 (Verilog is similar to C code in terms of comments and general rules, so we'll count as C code here).
Here's the code size as calculated with cloc --force-lang="C" *.v:
36 text files. 6 unique files. 0 files ignored. http://cloc.sourceforge.net v 1.56 T=0.5 s (72.0 files/s, 31542.0 lines/s) ------------------------------------------------------------------------------- Language files blank comment code ------------------------------------------------------------------------------- C 36 2074 2502 11195 ------------------------------------------------------------------------------- SUM: 36 2074 2502 11195 -------------------------------------------------------------------------------
This work is intended to be open source, but because there are no obviously appropriate licenses to achieve copy left for hardware designs (ultimately what RTL code becomes in ASICs - it's less obvious what it becomes in FPGAs) it's licensed under the Open Hardware Description License which I (Julius) made up out of the Mozilla Public License 2.0.
I want a weak copy-left hardware so ASIC designers can collaborate with us without fear of having to divulge the proprietary portions of the chip, which a strong copy-left license would require. Getting something back is better than getting nothing back.
If you don't like it, my license lets you relicense this work under the GPLs (are you crazy?!) or the more considered CERN OHL.
Licensing rant over.