grapefruit: add spd proxy passthrough (#313)

This plops down the SPD block in grapefruit with the commands to the
internal FPGA controller disabled, effectively making it a CPU<->DIMM
passthrough (exercising the SDA arbitration logic at low speeds, at
least). The ruby boots with this image in place (all the activity shows
the reworked G channel 0 ACKing and all the ensuing traffic):

![image](https://github.com/user-attachments/assets/622eac46-1b8c-4568-83dc-f43704f0cb7c)

I get to nanoblrs successfully.

My plan is to merge this and get it put into @citrus-it's Hubris dev
branch. This means no more shuffling DIMMs around for you
@nathanaelhuffman!

Author: Aaron-Hartwig

hdl/projects/grapefruit/BUCK

@@ -73,13 +73,17 @@ vhdl_unit(
         ":gfruit_sgpio",
         ":gfruit_black_boxes",
         "//hdl/projects/cosmo_seq:reset_sync",
+        "//hdl/projects/cosmo_seq/spd_proxy:spd_proxy_top",
+        "//hdl/ip/vhd/i2c/common:i2c_common_pkg",
         "//hdl/ip/vhd/info:info",
         "//hdl/ip/vhd/espi:espi_top",
         "//hdl/ip/vhd/uart:axi_fifo_uart",
         "//hdl/ip/vhd/axi_blocks:axil_interconnect",
         "//hdl/ip/vhd/spi_nor_controller:spi_nor_top",
         "//hdl/ip/vhd/fmc_if:stm32h7_fmc_target",
+        "//hdl/ip/vhd/common:streaming_if_pkg",
         "//hdl/ip/vhd/common:time_pkg",
+        "//hdl/ip/vhd/common:tristate_if_pkg",
     ],
     standard = "2019",
 )

hdl/projects/grapefruit/grapefruit_pins.xdc

@@ -130,16 +130,20 @@ set_property -dict { PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports { espi_hpm_
 set_property SLEW FAST [get_ports espi_hpm_to_scm_dat[*]]
 set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_abcdef_scl }];
 set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_abcdef_sda }];
-set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_ghijkl_scl }];
-set_property -dict { PACKAGE_PIN Y5 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm0_ghijkl_sda }];
+# we have pullups applied to the i3c_hpm_to_scm_dimm0_ghijkl bus for experimentation getting the SPD
+# proxying working with Ruby in a setup that requires a bit of rework.
+set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports { i3c_hpm_to_scm_dimm0_ghijkl_scl }];
+set_property -dict { PACKAGE_PIN Y5 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports { i3c_hpm_to_scm_dimm0_ghijkl_sda }];
 set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm1_abcdef_scl }];
 set_property -dict { PACKAGE_PIN AA3 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm1_abcdef_sda }];
 set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm1_ghijkl_scl }];
 set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVCMOS18 } [get_ports { i3c_hpm_to_scm_dimm1_ghijkl_sda }];
 set_property -dict { PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm0_abcdef_scl }];
 set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm0_abcdef_sda }];
-set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm0_ghijkl_scl }];
-set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm0_ghijkl_sda }];
+# we have pullups applied to the i3c_scm_to_dimm0_ghijkl bus for experimentation getting the SPD
+# proxying working with Ruby in a setup that requires a bit of rework.
+set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports { i3c_scm_to_dimm0_ghijkl_scl }];
+set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports { i3c_scm_to_dimm0_ghijkl_sda }];
 set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm1_abcdef_scl }];
 set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm1_abcdef_sda }];
 set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { i3c_scm_to_dimm1_ghijkl_scl }];

hdl/projects/grapefruit/grapefruit_top.vhd

@@ -13,7 +13,10 @@ use ieee.numeric_std_unsigned.all;
 use work.axil_common_pkg.all;
 use work.axil26x32_pkg;
 use work.axil8x32_pkg;
+use work.i2c_common_pkg.all;
+use work.stream8_pkg;
 use work.time_pkg.all;
+use work.tristate_if_pkg.all;
 
 entity grapefruit_top is
     port (
@@ -244,7 +247,14 @@ architecture rtl of grapefruit_top is
     signal sp5_owns_flash : std_logic;
     signal spi_nor_block_data_o : std_logic_vector(3 downto 0);
     signal spi_nor_block_data_oe : std_logic_vector(3 downto 0);
-   
+
+    signal ruby_scl_if : tristate;
+    signal ruby_sda_if : tristate;
+    signal dimm_scl_if : tristate;
+    signal dimm_sda_if : tristate;
+    -- stubs
+    signal i2c_tx_st_if : stream8_pkg.data_channel;
+    signal i2c_rx_st_if : stream8_pkg.data_channel;
 begin
 
     espi_scm_to_hpm_alert_l <= 'Z';
@@ -568,26 +578,36 @@ begin
         sgpio1_ld => sgpio_scm_to_hpm_ld(1)
     );
 
-    i3c_hpm_to_scm_dimm0_abcdef_scl <= not counter(26);
-    i3c_hpm_to_scm_dimm0_abcdef_sda <= not counter(26);
-
-    i3c_hpm_to_scm_dimm1_abcdef_scl <= not counter(26);
-    i3c_hpm_to_scm_dimm1_abcdef_sda <= not counter(26);
-    i3c_hpm_to_scm_dimm1_ghijkl_scl <= not counter(26);
-    i3c_hpm_to_scm_dimm1_ghijkl_sda <= not counter(26);
-
-    i3c_scm_to_dimm0_abcdef_scl <= not counter(26);
-    i3c_scm_to_dimm0_abcdef_sda <= not counter(26);
-    
-    i3c_scm_to_dimm1_abcdef_scl <= not counter(26);
-    i3c_scm_to_dimm1_abcdef_sda <= not counter(26);
-    i3c_scm_to_dimm1_ghijkl_scl <= not counter(26);
-    i3c_scm_to_dimm1_ghijkl_sda <= not counter(26);
-
-    -- these signals are intentionally left unused due to the ruby rework on sapphire
-    -- i3c_hpm_to_scm_dimm0_ghijkl_scl
-    -- i3c_hpm_to_scm_dimm0_ghijkl_sda
-    -- i3c_scm_to_dimm0_ghijkl_scl
-    -- i3c_scm_to_dimm0_ghijkl_sda
+    -- Ruby -> Grapefruit bus (filtered in SPD block)
+    i3c_hpm_to_scm_dimm0_ghijkl_scl <= ruby_scl_if.o when ruby_scl_if.oe else 'Z';
+    ruby_scl_if.i   <= i3c_hpm_to_scm_dimm0_ghijkl_scl;
+    i3c_hpm_to_scm_dimm0_ghijkl_sda <= ruby_sda_if.o when ruby_sda_if.oe else 'Z';
+    ruby_sda_if.i   <= i3c_hpm_to_scm_dimm0_ghijkl_sda;
+
+    -- Grapefruit -> DIMM bus (filtered in SPD block)
+    i3c_scm_to_dimm0_ghijkl_scl <= dimm_scl_if.o when dimm_scl_if.oe else 'Z';
+    dimm_scl_if.i   <= i3c_scm_to_dimm0_ghijkl_scl;
+    i3c_scm_to_dimm0_ghijkl_sda <= dimm_sda_if.o when dimm_sda_if.oe else 'Z';
+    dimm_sda_if.i   <= i3c_scm_to_dimm0_ghijkl_sda;
+
+    -- Wiring this in with the i2c_cmd interface disabled so it will just pass through the CPU/DIMM
+    -- comminication for now.
+    spd_proxy_top_inst: entity work.spd_proxy_top
+        generic map(
+            CLK_PER_NS  => 8, -- clk @ 125MHz = 8ns period
+            I2C_MODE    => FAST_PLUS
+        )
+        port map(
+            clk                 => clk_125m,
+            reset               => reset_125m,
+            cpu_scl_if          => ruby_scl_if,
+            cpu_sda_if          => ruby_sda_if,
+            dimm_scl_if         => dimm_scl_if,
+            dimm_sda_if         => dimm_sda_if,
+            i2c_command         => CMD_RESET,
+            i2c_command_valid   => '0',
+            i2c_tx_st_if        => i2c_tx_st_if,
+            i2c_rx_st_if        => i2c_rx_st_if
+        );
 
 end rtl;