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Aaron-HartwigAaron-Hartwig
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make SDA aribtration logic its own module (#311)
This could be parameterized further to be a more general way to arbitrate a shared bus where the FPGA is a proxy, but for now this is what it is.
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‎hdl/projects/cosmo_seq/spd_proxy/BUCK‎

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load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
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vhdl_unit(
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name = "sda_arbiter",
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srcs = glob(["sda_arbiter/*.vhd"]),
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deps = [],
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visibility = ['PUBLIC'],
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)
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vhdl_unit(
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name = "spd_proxy_top",
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srcs = glob(["*.vhd"]),
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deps = [
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":sda_arbiter",
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"//hdl/ip/vhd/common:tristate_if_pkg",
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"//hdl/ip/vhd/i2c/common:i2c_common_pkg",
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"//hdl/ip/vhd/i2c/common:i2c_glitch_filter",
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"//hdl/ip/vhd/i2c/controller:i2c_ctrl_txn_layer",
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],
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standard = "2019",
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visibility = ['PUBLIC']
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visibility = ['PUBLIC'],
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)
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vunit_sim(
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name = "sda_arbiter_tb",
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srcs = glob(["sda_arbiter/sims/*.vhd"]),
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deps = [
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":sda_arbiter",
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],
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visibility = ['PUBLIC'],
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)
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vunit_sim(

‎hdl/projects/cosmo_seq/spd_proxy/sda_arbiter/sda_arbiter.vhd‎

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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
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--
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-- Copyright 2025 Oxide Computer Company
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--
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-- This block monitors two I2C SDA signals, `a` and `b`, with the intention thatt hey are
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-- essentially connected but proxied by the FPGA. It assumes the inactive state for the bus is high,
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-- and then monitors for `a` or `b` to pull the line low. It will then grant whichever side pulled
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-- the line low the bus until that side releases it, at which point after HYSTERESIS_CYCLES both
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-- sides will be resampled again.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sda_arbiter is
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generic (
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HYSTERESIS_CYCLES : natural
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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a : in std_logic;
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b : in std_logic;
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enabled : in std_logic;
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a_grant : out std_logic;
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b_grant : out std_logic
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);
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end entity;
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architecture rtl of sda_arbiter is
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type sda_control_t is (
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NONE,
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GRANT_A,
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GRANT_B
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);
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signal sda_state : sda_control_t;
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signal hysteresis_cntr : natural range 0 to HYSTERESIS_CYCLES;
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begin
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a_grant <= '1' when sda_state = GRANT_A else '0';
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b_grant <= '1' when sda_state = GRANT_B else '0';
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arbitration : process(clk, reset)
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variable sda_next : sda_control_t;
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begin
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if reset then
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sda_state <= NONE;
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hysteresis_cntr <= 0;
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elsif rising_edge(clk) then
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if enabled then
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if hysteresis_cntr = HYSTERESIS_CYCLES then
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case sda_state is
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when NONE =>
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if a = '0' and b = '1' then
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sda_next := GRANT_A;
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elsif a = '1' and b = '0' then
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sda_next := GRANT_B;
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end if;
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when GRANT_A =>
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if a = '1' then
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sda_next := NONE;
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end if;
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when GRANT_B =>
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if b = '1' then
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sda_next := NONE;
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end if;
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end case;
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-- arbitration changed, enforce hysteresis
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if sda_next /= sda_state then
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hysteresis_cntr <= 0;
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end if;
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else
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hysteresis_cntr <= hysteresis_cntr + 1;
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end if;
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else
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sda_next := NONE;
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hysteresis_cntr <= 0;
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end if;
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sda_state <= sda_next;
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end if;
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end process;
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end architecture;

‎hdl/projects/cosmo_seq/spd_proxy/sda_arbiter/sims/sda_arbiter_tb.gtkw‎

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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Mon Mar 17 12:06:15 2025
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[*]
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[dumpfile] "/home/aaron/Oxide/git/quartz/vunit_out/test_output/lib.sda_arbiter_tb.hysteresis_fba39672ff868058b296cfd50da9181a1eabe178/nvc/sda_arbiter_tb.fst"
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[dumpfile_mtime] "Mon Mar 17 12:06:00 2025"
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[dumpfile_size] 767
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[savefile] "/home/aaron/Oxide/git/quartz/hdl/projects/cosmo_seq/spd_proxy/sda_arbiter/sims/sda_arbiter_tb.gtkw"
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[timestart] 0
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[size] 2528 1283
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[pos] 1138 -22
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*-25.222696 100000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] sda_arbiter_tb.
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[sst_width] 221
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[signals_width] 313
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[sst_expanded] 1
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[sst_vpaned_height] 382
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@28
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sda_arbiter_tb.sda_arbiter_inst.clk
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sda_arbiter_tb.sda_arbiter_inst.reset
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sda_arbiter_tb.sda_arbiter_inst.enabled
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sda_arbiter_tb.sda_arbiter_inst.a
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sda_arbiter_tb.sda_arbiter_inst.b
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sda_arbiter_tb.sda_arbiter_inst.sda_state
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@25
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sda_arbiter_tb.sda_arbiter_inst.hysteresis_cntr
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@28
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sda_arbiter_tb.sda_arbiter_inst.a_grant
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sda_arbiter_tb.sda_arbiter_inst.b_grant
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[pattern_trace] 1
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[pattern_trace] 0

‎hdl/projects/cosmo_seq/spd_proxy/sda_arbiter/sims/sda_arbiter_tb.vhd‎

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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
4+
--
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-- Copyright 2025 Oxide Computer Company
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7+
library ieee;
8+
use ieee.std_logic_1164.all;
9+
use ieee.numeric_std_unsigned.all;
10+
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library vunit_lib;
12+
context vunit_lib.com_context;
13+
context vunit_lib.vunit_context;
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entity sda_arbiter_tb is
16+
generic (
17+
runner_cfg : string
18+
);
19+
end entity;
20+
21+
architecture tb of sda_arbiter_tb is
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constant CLK_PER_TIME : time := 8 ns;
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constant HYSTERESIS_CYCLES : integer := 10;
24+
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
27+
signal a : std_logic := '1';
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signal b : std_logic := '1';
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signal enabled : std_logic := '1';
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signal a_grant : std_logic;
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signal b_grant : std_logic;
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begin
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clk <= not clk after CLK_PER_TIME / 2;
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reset <= '0' after 100 ns;
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sda_arbiter_inst: entity work.sda_arbiter
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generic map(
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HYSTERESIS_CYCLES => HYSTERESIS_CYCLES
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)
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port map(
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clk => clk,
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reset => reset,
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a => a,
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b => b,
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enabled => enabled,
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a_grant => a_grant,
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b_grant => b_grant
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);
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bench: process
52+
variable cycle_counter : integer := 0;
53+
begin
54+
-- Always the first thing in the process, set up things for the VUnit test runner
55+
test_runner_setup(runner, runner_cfg);
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-- wait for reset to clear
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wait until reset = '0';
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while test_suite loop
61+
if run("grant_a") then
62+
-- assert A bus
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b <= '1';
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wait for 100 ns;
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a <= '0';
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check_true(a_grant = '0', "Bus A should not be granted the bus.");
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check_true(b_grant = '0', "Bus B should not be granted the bus.");
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-- arbitration grant is registered
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wait for CLK_PER_TIME + 1 ns;
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check_true(a_grant = '1', "Bus A should immediately be granted the bus.");
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check_true(b_grant = '0', "Bus B should not be granted the bus.");
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elsif run("grant_b") then
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-- assert B bus
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a <= '1';
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wait for 100 ns;
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b <= '0';
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check_true(a_grant = '0', "Bus A should not be granted the bus.");
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check_true(b_grant = '0', "Bus B should not be granted the bus.");
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-- arbitration grant is registered
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wait for CLK_PER_TIME + 1 ns;
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check_true(a_grant = '0', "Bus A should not be granted the bus.");
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check_true(b_grant = '1', "Bus B should immediately be granted the bus.");
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elsif run("hysteresis") then
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-- assert A bus
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b <= '1';
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wait for 100 ns;
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a <= '0';
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wait until a_grant = '1';
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-- release A bus and assert B bus, expecting the arbitration not to change before
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-- HYSTERESIS_CYCLES has passed
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a <= '1';
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b <= '0';
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while cycle_counter <= HYSTERESIS_CYCLES loop
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wait for CLK_PER_TIME;
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check_true(a_grant = '1', "Bus A should be granted the bus.");
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check_true(b_grant = '0', "Bus B should not be granted the bus.");
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cycle_counter := cycle_counter + 1;
106+
end loop;
107+
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-- after the initial hysteresis period, neither bus should be granted arbitration
109+
cycle_counter := 0;
110+
while cycle_counter <= HYSTERESIS_CYCLES loop
111+
wait for CLK_PER_TIME;
112+
check_true(a_grant = '0', "Bus A should not be granted the bus.");
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check_true(b_grant = '0', "Bus B should not be granted the bus.");
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cycle_counter := cycle_counter + 1;
115+
end loop;
116+
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-- after the second hysteresis period, B should be granted the bus.
118+
wait until rising_edge(clk);
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check_true(a_grant = '0', "Bus A should not be granted the bus.");
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check_true(b_grant = '1', "Bus B should be granted the bus.");
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elsif run("disable") then
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-- assert A bus
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b <= '1';
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wait for 100 ns;
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a <= '0';
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wait until a_grant = '1';
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enabled <= '0';
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wait for CLK_PER_TIME + 1 ns;
130+
check_true(a_grant = '0', "Bus A should not be granted the bus.");
131+
check_true(b_grant = '0', "Bus B should not be granted the bus.");
132+
end if;
133+
end loop;
134+
135+
wait for 1 us;
136+
test_runner_cleanup(runner);
137+
wait;
138+
end process;
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140+
test_runner_watchdog(runner, 10 us);
141+
end architecture;

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