Changed required for cosmo rev2 sequencer stuff (#425)

A few new pins, a few choices made based on revision pins to enable
functionality so that we can use rev2 and rev1 boards with the same FPGA image.

Author: nathanaelhuffman

hdl/projects/cosmo_seq/board_support/board_support_top.vhd

@@ -29,6 +29,8 @@ entity board_support is
         hubris_compat_ver : in std_logic_vector(2 downto 0);
         -- AXI interface for the "info" block
         info_axi_if : view axil_target;
+        is_rev1 : out std_logic;  -- tied high if rev1 board
+        is_rev2 : out std_logic  -- tied high if rev2 board
     );
 end entity;
 
@@ -41,6 +43,17 @@ architecture rtl of board_support is
 
 begin
 
+    -- Tie off the board revision outputs
+    -- skipping meta sync here b/c stuff is strapped on board.
+    -- Providing registers here since there could be some fan-out.
+    rev_indicators: process(clk_125m)
+    begin
+        if rising_edge(clk_125m) then
+            is_rev1 <= '1' when unsigned(hubris_compat_ver) = 0 else '0';  -- rev1 board
+            is_rev2 <= '1' when unsigned(hubris_compat_ver) = 1 else '0';  -- rev2 board
+        end if;
+    end process;
+
     -- We have a reset pin coming in from the SP.  Synchronize it first
     -- using the "raw" board clock, pre-PLL. We'll use this as the 
     -- reset to the PLL, and the aclr the down-stream clocks

hdl/projects/cosmo_seq/cosmo_seq_pins.xdc

@@ -281,3 +281,12 @@ set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { vddio_sp
 set_property -dict { PACKAGE_PIN C8 IOSTANDARD LVCMOS33 } [get_ports { vr_v1p8_sys_to_fpga1_alert_l }];
 set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vr_v3p3_sys_to_fpga1_alert_l }];
 set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { vr_v5p0_sys_to_fpga1_alert_l }];
+# New pins for cosmo rev2 only
+set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS33 } [get_ports { i2c_sp5_sec_v3p3_scl }];
+set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 } [get_ports { i2c_sp5_sec_v3p3_sda }];
+set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS18 } [get_ports { v1p1_i3c_a2_pg }];
+set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { v1p4_nic_a0hp_pg }];
+set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS33 } [get_ports { uart_fpga1_to_debug_dat }];
+set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports { uart_debug_to_fpga1_dat }];
+set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { uart_fpga1_to_debug_rts_l }];
+set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { uart_debug_to_fpga1_rts_l }];

hdl/projects/cosmo_seq/cosmo_seq_top.vhd

@@ -162,6 +162,8 @@ entity cosmo_seq_top is
         pwr_cont1_to_fpga1_vddio_sp5_pg : in std_logic;
         pwr_fpga1_to_v1p5_sp5_rtc_a2_en : out std_logic;
         pwr_v1p5_sp5_rtc_a2_to_fpga1_pg : in std_logic;
+        v1p1_i3c_a2_pg : in std_logic; -- only rev2+
+        v1p4_nic_a0hp_pg : in std_logic; -- only rev2+
         sp5_to_fpga1_pwrgd_out : in std_logic; -- spare readback from SP5
         sp5_to_fpga1_pwrok_unbuf : in std_logic;
         sp5_to_fpga1_slp_s3_l : in std_logic;
@@ -253,6 +255,9 @@ entity cosmo_seq_top is
         -- I2C SP mux stuff
         i2c_sp_to_fpga1_scl : inout std_logic;
         i2c_sp_to_fpga1_sda : inout std_logic;
+        --I2C SP5 SEC stuff (rev2+ only)
+        i2c_sp5_sec_v3p3_scl : inout std_logic;
+        i2c_sp5_sec_v3p3_sda : inout std_logic;
 
         fpga1_to_i2c_mux1_sel : out std_logic_vector(1 downto 0);
         fpga1_to_i2c_mux2_sel : out std_logic_vector(1 downto 0);
@@ -301,6 +306,12 @@ entity cosmo_seq_top is
         uart_local_sp_to_fpga1_dat : in std_logic;
         uart_local_sp_to_fpga1_rts_l : in std_logic;
 
+        -- Dedicated UART connector rev2+
+        uart_fpga1_to_debug_dat : out std_logic;
+        uart_debug_to_fpga1_dat : in std_logic;
+        uart_fpga1_to_debug_rts_l : out std_logic;
+        uart_debug_to_fpga1_rts_l : in std_logic;
+
         -- What to do with this stuff?, some maybe removed?
         v1p2_fpga2_a2_pg : in std_logic;
         v2p5_fpga2_a2_pg : in std_logic;
@@ -392,6 +403,11 @@ architecture rtl of cosmo_seq_top is
     signal allow_backplane_pcie_clk : std_logic;
     signal nic_dbg_pins : t6_debug_if;
     signal reg_alert_l_pins : seq_power_alert_pins_t;
+    signal is_rev1 : std_logic;
+    signal dbg_pins_uart_out : std_logic;
+    signal dbg_pins_uart_out_rts_l : std_logic;
+    signal dbg_pins_uart_in : std_logic;
+    signal dbg_pins_uart_in_rts_l : std_logic;
 
 begin
 
@@ -401,6 +417,10 @@ begin
         clk => clk_125m,
         sycnd_output => fpga2_hp_irq_n
     );
+
+    -- SP5 SEC (not available on rev1 cosmo, not yet implemented for rev2!)
+    i2c_sp5_sec_v3p3_scl <= 'Z';
+    i2c_sp5_sec_v3p3_sda <= 'Z';
     -- misc things tied:
     fpga1_to_fpga2_io <= (others => 'Z');
     fpga1_to_sp5_sys_reset_l <= 'Z';  -- We don't use this in product, external PU.
@@ -412,8 +432,14 @@ begin
     fpga1_uart0_buff_oe_en_l <= '0' when a0_ok else '1';
     fpga1_uart1_buff_oe_en_l <= '0' when a0_ok else '1'; -- not used but why not enable anyway?
     uart1_fpga1_to_sp5_dat_buff <= '1';  -- Make this idle generally, buffer protects from cross-drive
+    
     i3c_sp5_to_fpga1_oe_l <= '0' when  sp5_seq_pins.pwr_good else '1';
-    i3c_fpga1_to_dimm_oe_l <= '0' when  sp5_seq_pins.pwr_good else '1';
+    -- Rev1 cosmo board had a hw bug where one side of the i2c buffers was driven in an A1/A0 domain,
+    -- preventing access to the DDR SPD EEPROMs until the system was fully powered on. We gate rev1
+    -- board by the power-good (in A0) signal to prevent hanging the bus in that case, but rev2+ boards
+    -- don't have this problem so we can immediately enable them regardless of the SP5 power state which
+    -- is the desired system behavior.
+    i3c_fpga1_to_dimm_oe_l <= '0' when  (not is_rev1) or sp5_seq_pins.pwr_good else '1';
 
     ---------------------------------------------
     -- FMC to AXI Interface from the SP
@@ -468,7 +494,8 @@ begin
         reset_fmc => reset_fmc,
         fpga1_status_led => fpga1_status_led,
         hubris_compat_ver => seq_rev_id,
-        info_axi_if => responders(INFO_RESP_IDX)
+        info_axi_if => responders(INFO_RESP_IDX),
+        is_rev1 => is_rev1  -- tied high if rev1 board
     );
 
     -- espi and flash interface block
@@ -538,12 +565,40 @@ begin
         ipcc_from_espi => ipcc_uart_from_espi_axi_st,
         ipcc_to_espi => ipcc_uart_to_espi_axi_st,
         -- 
-        dbg_pins_uart_out => fpga1_spare_v3p3_7,
-        dbg_pins_uart_out_rts_l => fpga1_spare_v3p3_4,
-        dbg_pins_uart_in => fpga1_spare_v3p3_5,
-        dbg_pins_uart_in_rts_l => fpga1_spare_v3p3_6
+        dbg_pins_uart_out => dbg_pins_uart_out,
+        dbg_pins_uart_out_rts_l => dbg_pins_uart_out_rts_l,
+        dbg_pins_uart_in => dbg_pins_uart_in,
+        dbg_pins_uart_in_rts_l => dbg_pins_uart_in_rts_l
     );
 
+    -- Cosmo UART debug mux.
+    -- Comso rev2+ has a dedicated UART port on the board, use that for rev2+
+    process(all)
+    begin
+        if is_rev1 then
+            -- Use spare dbg pins for UART
+            fpga1_spare_v3p3_6 <= dbg_pins_uart_in_rts_l;
+            fpga1_spare_v3p3_7 <= dbg_pins_uart_out;
+            dbg_pins_uart_in <= fpga1_spare_v3p3_5;
+            dbg_pins_uart_out_rts_l <= fpga1_spare_v3p3_4;
+            -- Un-used and unaccessible in rev1
+            uart_fpga1_to_debug_dat <= 'Z';
+            uart_fpga1_to_debug_rts_l <= 'Z';
+        else
+            -- Give a tri-state driver here to prevent latches
+            fpga1_spare_v3p3_6 <= 'Z';
+            fpga1_spare_v3p3_7 <= 'Z';
+            -- Dedicated UART connector rev2+
+            uart_fpga1_to_debug_dat <= dbg_pins_uart_out;
+            dbg_pins_uart_in <= uart_debug_to_fpga1_dat;
+            uart_fpga1_to_debug_rts_l <= dbg_pins_uart_in_rts_l;
+            dbg_pins_uart_out_rts_l <= uart_debug_to_fpga1_rts_l;
+
+        end if;
+
+    end process;
+
+
     -- SP I2C muxes
     -- i2c is the only input, sycn'd inside the mux block(s)
     sp_i2c_subsystem_inst: entity work.sp_i2c_subsystem
@@ -798,6 +853,9 @@ begin
         -- sp
         i2c_sp_to_fpga1_scl => i2c_sp_to_fpga1_scl,
         i2c_sp_to_fpga1_sda => i2c_sp_to_fpga1_sda,
+        -- sp5 i2c
+        i2c_sp5_sec_to_fpga1_scl => i2c_sp5_sec_v3p3_scl,
+        i2c_sp5_sec_to_fpga1_sda => i2c_sp5_sec_v3p3_sda,
         -- dimms
         i3c_sp5_to_fpga1_abcdef_scl => i3c_sp5_to_fpga1_abcdef_scl,
         i3c_sp5_to_fpga1_abcdef_sda => i3c_sp5_to_fpga1_abcdef_sda,

hdl/projects/cosmo_seq/debug_module/debug_header.vhd

@@ -25,6 +25,9 @@ entity debug_header is
         -- sp
         i2c_sp_to_fpga1_scl: in std_logic;
         i2c_sp_to_fpga1_sda: in std_logic;
+        -- sp5 sec i2c
+        i2c_sp5_sec_to_fpga1_scl : in std_logic;
+        i2c_sp5_sec_to_fpga1_sda : in std_logic;
         -- dimms
         i3c_sp5_to_fpga1_abcdef_scl: in std_logic;
         i3c_sp5_to_fpga1_abcdef_sda: in std_logic;
@@ -74,6 +77,8 @@ architecture rtl of debug_header is
     signal i3c_fpga1_to_dimm_abcdef_sda_int: std_logic;
     signal i3c_fpga1_to_dimm_ghijkl_scl_int: std_logic;
     signal i3c_fpga1_to_dimm_ghijkl_sda_int: std_logic;
+    signal i2c_sp5_sec_to_fpga1_scl_int :std_logic;
+    signal i2c_sp5_sec_to_fpga1_sda_int : std_logic;
     signal uart1_sp_to_fpga1_dat_int : std_logic;
     signal uart1_fpga1_to_sp_dat_int : std_logic;
     signal uart0_sp_to_fpga1_dat_int : std_logic;
@@ -101,6 +106,8 @@ sample_reg: process(clk_200m, reset_200m)
             i2c_sp_to_fpga1_scl_int <= i2c_sp_to_fpga1_scl;
             i2c_sp5_to_fpgax_hp_sda_int <= i2c_sp5_to_fpgax_hp_sda;
             i2c_sp5_to_fpgax_hp_scl_int <= i2c_sp5_to_fpgax_hp_scl;
+            i2c_sp5_sec_to_fpga1_scl_int <= i2c_sp5_sec_to_fpga1_scl;
+            i2c_sp5_sec_to_fpga1_sda_int <= i2c_sp5_sec_to_fpga1_sda;
             i3c_sp5_to_fpga1_abcdef_scl_int <= i3c_sp5_to_fpga1_abcdef_scl; 
             i3c_sp5_to_fpga1_abcdef_sda_int <= i3c_sp5_to_fpga1_abcdef_sda; 
             i3c_sp5_to_fpga1_ghijkl_scl_int <= i3c_sp5_to_fpga1_ghijkl_scl; 
@@ -202,6 +209,9 @@ hdr_dbg_reg_1v8: process(clk_200m, reset_200m)
                     -- Mux3 select pins
                     fpga1_spare_reg(7) <= mux3_sel_int(1);
                     fpga1_spare_reg(6) <= mux3_sel_int(0);
+                when I2C_SP5_SEC_BUS =>
+                    fpga1_spare_reg(7) <= i2c_sp5_sec_to_fpga1_scl_int;
+                    fpga1_spare_reg(6) <= i2c_sp5_sec_to_fpga1_sda_int;
                 when others =>
                     -- Default case, do nothing
                     fpga1_spare_reg(7 downto 6) <= (others => '0');
@@ -254,6 +264,9 @@ hdr_dbg_reg_1v8: process(clk_200m, reset_200m)
                     -- Mux3 select pins
                     fpga1_spare_reg(5) <= mux3_sel_int(1);
                     fpga1_spare_reg(4) <= mux3_sel_int(0);
+                 when I2C_SP5_SEC_BUS =>
+                    fpga1_spare_reg(5) <= i2c_sp5_sec_to_fpga1_scl_int;
+                    fpga1_spare_reg(4) <= i2c_sp5_sec_to_fpga1_sda_int;
                 when others =>
                     -- Default case, do nothing
                     fpga1_spare_reg(5 downto 4) <= (others => '0');
@@ -302,6 +315,9 @@ hdr_dbg_reg_1v8: process(clk_200m, reset_200m)
                 when MUX3_SEL =>
                     fpga1_spare_reg(3) <= mux3_sel_int(1);
                     fpga1_spare_reg(2) <= mux3_sel_int(0);
+                when I2C_SP5_SEC_BUS =>
+                    fpga1_spare_reg(3) <= i2c_sp5_sec_to_fpga1_scl_int;
+                    fpga1_spare_reg(2) <= i2c_sp5_sec_to_fpga1_sda_int;
                 when others =>
                     -- Default case, do nothing
                     fpga1_spare_reg(3 downto 2) <= (others => '0');
@@ -351,6 +367,9 @@ hdr_dbg_reg_1v8: process(clk_200m, reset_200m)
                 when MUX3_SEL =>
                     fpga1_spare_reg(1) <= mux3_sel_int(1);
                     fpga1_spare_reg(0) <= mux3_sel_int(0);
+                 when I2C_SP5_SEC_BUS =>
+                    fpga1_spare_reg(1) <= i2c_sp5_sec_to_fpga1_scl_int;
+                    fpga1_spare_reg(0) <= i2c_sp5_sec_to_fpga1_sda_int;
                 when others =>
                     -- Default case, do nothing
                     fpga1_spare_reg(1 downto 0) <= (others => '0');

hdl/projects/cosmo_seq/debug_module/debug_module_top.vhd

@@ -36,6 +36,9 @@ entity debug_module_top is
         -- sp
         i2c_sp_to_fpga1_scl: in std_logic;
         i2c_sp_to_fpga1_sda: in std_logic;
+        -- sp5 sec i2c
+        i2c_sp5_sec_to_fpga1_scl : in std_logic;
+        i2c_sp5_sec_to_fpga1_sda : in std_logic;
         -- dimms
         i3c_sp5_to_fpga1_abcdef_scl: in std_logic;
         i3c_sp5_to_fpga1_abcdef_sda: in std_logic;
@@ -94,6 +97,8 @@ begin
         i2c_sp5_to_fpgax_hp_scl => i2c_sp5_to_fpgax_hp_scl,
         i2c_sp_to_fpga1_scl => i2c_sp_to_fpga1_scl,
         i2c_sp_to_fpga1_sda => i2c_sp_to_fpga1_sda,
+        i2c_sp5_sec_to_fpga1_scl => i2c_sp5_sec_to_fpga1_scl,
+        i2c_sp5_sec_to_fpga1_sda => i2c_sp5_sec_to_fpga1_sda,
         i3c_sp5_to_fpga1_abcdef_scl => i3c_sp5_to_fpga1_abcdef_scl,
         i3c_sp5_to_fpga1_abcdef_sda => i3c_sp5_to_fpga1_abcdef_sda,
         i3c_sp5_to_fpga1_ghijkl_scl => i3c_sp5_to_fpga1_ghijkl_scl,

hdl/projects/cosmo_seq/debug_module/debug_regs.rdl

@@ -127,6 +127,7 @@ addrmap debug_regs {
             mux1_sel = 8'h0c {desc = "Mux1 sel pins debug output to pins";};
             mux2_sel = 8'h0d {desc = "Mux2 sel pins debug output to pins";};
             mux3_sel = 8'h0e {desc = "Mux3 sel pins debug output to pins";};
+            i2c_sp5_sec_bus = 8'h0f {desc = "SP5 -> FPGA sec i2c bus to pins";};
         };
         field {
             desc = "Selects which debug output is sent to the 1v8 debug header in sets of two pins.