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Fix tests
1 parent 42917a9 commit 9a793d4

3 files changed

Lines changed: 7 additions & 30 deletions

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mypyc/test-data/irbuild-vec-i64.test

Lines changed: 5 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,6 @@ L5:
8686
return r6
8787

8888
[case testVecI64GetItem_32bit]
89-
# The IR is quite verbose, but it's acceptable since 32-bit targets are not common any more
9089
from librt.vecs import vec
9190
from mypy_extensions import i64
9291

@@ -102,13 +101,7 @@ def f(v, i):
102101
r3 :: i64
103102
r4 :: bit
104103
r5 :: bool
105-
r6 :: i64
106-
r7, r8 :: bit
107-
r9 :: native_int
108-
r10 :: ptr
109-
r11 :: native_int
110-
r12 :: ptr
111-
r13 :: i64
104+
r6, r7 :: i64
112105
L0:
113106
r0 = v.len
114107
r1 = extend signed r0: native_int to i64
@@ -127,24 +120,8 @@ L3:
127120
L4:
128121
r6 = i
129122
L5:
130-
r7 = r6 < 2147483648 :: signed
131-
if r7 goto L6 else goto L8 :: bool
132-
L6:
133-
r8 = r6 >= -2147483648 :: signed
134-
if r8 goto L7 else goto L8 :: bool
135-
L7:
136-
r9 = truncate r6: i64 to native_int
137-
goto L9
138-
L8:
139-
CPyInt32_Overflow()
140-
unreachable
141-
L9:
142-
r10 = v.items
143-
r11 = r9 * 8
144-
r12 = r10 + r11
145-
r13 = load_mem r12 :: i64*
146-
keep_alive v
147-
return r13
123+
r7 = vec_get_item_unsafe[i64] v, r6
124+
return r7
148125

149126
[case testVecI64Append]
150127
from librt.vecs import vec, append
@@ -403,7 +380,7 @@ L3:
403380
L4:
404381
return r1
405382

406-
[case testVecI64FastComprehensionFromVec]
383+
[case testVecI64FastComprehensionFromVec_64bit]
407384
from librt.vecs import vec
408385
from mypy_extensions import i64
409386
from typing import List
@@ -484,7 +461,7 @@ L3:
484461
L4:
485462
return r1
486463

487-
[case testVecI64ForLoop]
464+
[case testVecI64ForLoop_64bit]
488465
from librt.vecs import vec
489466
from mypy_extensions import i64
490467

mypyc/test-data/irbuild-vec-misc.test

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ L0:
202202
r0 = VecFloatApi.slice(v, x, y)
203203
return r0
204204

205-
[case testVecMiscForLoop]
205+
[case testVecMiscForLoop_64bit]
206206
from librt.vecs import vec, remove
207207

208208
from mypy_extensions import i64, i16

mypyc/test-data/irbuild-vec-t.test

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -511,7 +511,7 @@ L0:
511511
r2 = VecTApi.from_iterable(r1, a, 0)
512512
return r2
513513

514-
[case testVecTBorrowGetItem]
514+
[case testVecTBorrowGetItem_64bit]
515515
from librt.vecs import vec
516516
from mypy_extensions import i64
517517

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