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Move tiny-arm interfaces
1 parent 75711e8 commit c21bafb

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4 files changed

+38
-28
lines changed

4 files changed

+38
-28
lines changed

instrs-user.sail

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -114,13 +114,22 @@ function clause execute ExclusiveOr(d, n, m) = {
114114
}
115115

116116
/* Data Barrier */
117-
union clause ast = DataMemoryBarrier : MBReqTypes
118-
union clause ast = DataSynchronizationBarrier : MBReqTypes
117+
union clause ast = DataMemoryBarrier : (MBReqDomain, MBReqTypes)
118+
union clause ast = DataSynchronizationBarrier : (MBReqDomain, MBReqTypes)
119119
union clause ast = InstructionSynchronizationBarrier : unit
120120

121121
val decodeDataBarrier : (bits(4), bool) -> option(ast)
122122

123123
function decodeDataBarrier(CRm, is_sync) = {
124+
let domain : MBReqDomain =
125+
match CRm[3..2] {
126+
0b11 => MBReqDomain_FullSystem,
127+
0b10 => MBReqDomain_InnerShareable,
128+
0b01 => MBReqDomain_Nonshareable,
129+
0b00 => MBReqDomain_OuterShareable,
130+
_ => return None()
131+
};
132+
124133
let types : MBReqTypes =
125134
match CRm[1..0] {
126135
0b01 => MBReqTypes_Reads,
@@ -130,33 +139,33 @@ function decodeDataBarrier(CRm, is_sync) = {
130139
};
131140

132141
if is_sync then
133-
Some(DataSynchronizationBarrier(types))
142+
Some(DataSynchronizationBarrier(domain, types))
134143
else
135-
Some(DataMemoryBarrier(types))
144+
Some(DataMemoryBarrier(domain, types))
136145
}
137146

138147
/* DMB */
139148
function clause decode (0b1101010100@0b0@0b00@0b011@0b0011@(CRm : bits(4))@0b1@0b01@0b11111) = {
140149
decodeDataBarrier(CRm, false)
141150
}
142151

143-
function clause execute DataMemoryBarrier(types) = {
152+
function clause execute DataMemoryBarrier(domain, types) = {
144153
// Update the PC
145154
_PC = _PC + 4;
146155
// Then perform the barrier
147-
dataMemoryBarrier(types);
156+
dataMemoryBarrier(domain, types);
148157
}
149158

150159
/* DSB */
151160
function clause decode (0b11010101000000110011@(CRm:bits(4))@0b100@0b11111) = {
152161
decodeDataBarrier(CRm, true)
153162
}
154163

155-
function clause execute DataSynchronizationBarrier(types) = {
164+
function clause execute DataSynchronizationBarrier(domain, types) = {
156165
// Update the PC
157166
_PC = _PC + 4;
158167
// Then perform the barrier
159-
dataSynchronizationBarrer(types)
168+
dataSynchronizationBarrer(domain, types)
160169
}
161170

162171
/* ISB */
@@ -205,6 +214,3 @@ function clause execute CompareAndBranch(t, offset) = {
205214
}
206215
else _PC = _PC + 4;
207216
}
208-
209-
// This catch-all clause MUST be the last clause for the `decode` function.
210-
function clause decode(_) = { None() }

interface.sail

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,17 @@ $include <concurrency_interface/exception.sail>
44
$include <concurrency_interface/cache_op.sail>
55
$include <concurrency_interface/translation.sail>
66

7+
scattered union ast
8+
9+
val decode : bits(32) -> option(ast)
10+
scattered function decode
11+
12+
val execute : ast -> unit
13+
scattered function execute
14+
15+
// Simple top level fetch and execute loop.
16+
val fetch_and_execute : unit -> unit
17+
718
$ifdef SYSTEM_TINY_ARM
819
type addr_size : Int = 56
920
let addr_size' : int(56) = 56
@@ -299,8 +310,8 @@ val iFetch : (bits(addr_size), AccessDescriptor) -> bits(32)
299310
val rMem : (bits(addr_size), AccessDescriptor) -> bits(64)
300311
val wMem_Addr : bits(addr_size) -> unit
301312
val wMem : (bits(addr_size), bits(64), AccessDescriptor) -> unit
302-
val dataMemoryBarrier : MBReqTypes -> unit
303-
val dataSynchronizationBarrer : MBReqTypes -> unit
313+
val dataMemoryBarrier : (MBReqDomain, MBReqTypes) -> unit
314+
val dataSynchronizationBarrer : (MBReqDomain, MBReqTypes) -> unit
304315
val instructionSynchronizationBarrier : unit -> unit
305316

306317
val translate_address : (bits(64), AccessDescriptor) -> option(bits(addr_size))
@@ -346,15 +357,15 @@ function wMem(addr, value, accdesc) = {
346357
instantiation sail_barrier with
347358
'barrier = Barrier
348359

349-
function dataMemoryBarrier(types) = sail_barrier(
360+
function dataMemoryBarrier(domain, types) = sail_barrier(
350361
Barrier_DMB(struct{
351-
domain = MBReqDomain_InnerShareable,
362+
domain = domain,
352363
types = types,
353364
nXS = false}))
354365

355-
function dataSynchronizationBarrer(types) = sail_barrier(
366+
function dataSynchronizationBarrer(domain, types) = sail_barrier(
356367
Barrier_DSB(struct{
357-
domain = MBReqDomain_InnerShareable,
368+
domain = domain,
358369
types = types,
359370
nXS = false}))
360371

sail_files

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,6 @@ interface_types.sail
33
registers.sail
44
interface.sail
55
translation.sail
6-
tiny-arm.sail
7-
instrs-sys.sail
86
instrs-user.sail
7+
instrs-sys.sail
8+
tiny-arm.sail

tiny-arm.sail

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,6 @@
1-
scattered union ast
1+
// This catch-all clause MUST be the last clause for the `decode` function.
2+
function clause decode(_) = { None() }
23

3-
val decode : bits(32) -> option(ast)
4-
scattered function decode
5-
6-
val execute : ast -> unit
7-
scattered function execute
8-
9-
// Simple top level fetch and execute loop.
10-
val fetch_and_execute : unit -> unit
114

125
function fetch_and_execute () = {
136
let accdesc = create_iFetchAccessDescriptor();

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