Many missing register fields (and RES1 handling query)

[gr1mpatr0n]

SCTLR_EL1::SPAN minimally is missing, which is necessary for implementation of a trusted OS at S-EL1.

However, looking closer, it seems all positions between bits 20 and 23 are missing. So: SPAN, EIS, IESB, TSCXT. I'm guessing the story is the same for the other ELx versions of this register.

In the longer term, it would be great to see register definitions be derived automatically from Arm's published machine-readable specification packages (the "SysReg" MRS package).

Also, I couldn't seem to see the RES1 fields handled anywhere, e.g. for TCR_EL1, so I had to hardcode those manually. It would be good if the Writeable trait impl managed that for you.

[gr1mpatr0n]

Hmm OK, so it seems this is the approach arm-sysregs takes. I would hope that converting the machine readable format into a tock-registers register_bitfields! stanza would likely be possible without too much pain - so I will keep this issue open for prosperity.

There are several tradeoffs with arm-sysregs. It does not for example, provide defines for memory attributes, only for indexing the MAIR. Shame there doesn't seem to be a single comprehensive crate.