Reimplement architecture selection

Author: nathan-TT

bfd/archures.c

@@ -447,9 +447,6 @@ DESCRIPTION
 .  bfd_arch_riscv,
 .#define bfd_mach_riscv32	132
 .#define bfd_mach_riscv64	164
-.#define bfd_mach_riscv32_sfpu	1320
-.#define bfd_mach_riscv32_sfpu_wormhole	1321
-.#define bfd_mach_riscv32_sfpu_blackhole 1322
 .  bfd_arch_rl78,
 .#define bfd_mach_rl78		0x75
 .  bfd_arch_rx,	       {* Renesas RX.  *}

bfd/bfd-in2.h

@@ -1774,9 +1774,6 @@ enum bfd_architecture
   bfd_arch_riscv,
 #define bfd_mach_riscv32       132
 #define bfd_mach_riscv64       164
-#define bfd_mach_riscv32_sfpu  1320
-#define bfd_mach_riscv32_sfpu_wormhole  1321
-#define bfd_mach_riscv32_sfpu_blackhole  1322
   bfd_arch_rl78,
 #define bfd_mach_rl78          0x75
   bfd_arch_rx,        /* Renesas RX.  */
@@ -7928,7 +7925,6 @@ bool bfd_init_section_compress_status
 bool bfd_compress_section
    (bfd *abfd, asection *section, bfd_byte *uncompressed_buffer);
 
-extern int riscv_machine_target;
 #ifdef __cplusplus
 }
 #endif

bfd/cpu-riscv.c

@@ -87,9 +87,6 @@ enum
 {
   I_riscv64,
   I_riscv32,
-  I_riscv32_sfpu_blackhole,
-  I_riscv32_sfpu_wormhole,
-  I_riscv32_sfpu
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -99,10 +96,7 @@ enum
 static const bfd_arch_info_type arch_info_struct[] =
 {
   N (64, bfd_mach_riscv64, "riscv:rv64", false, NN (I_riscv64)),
-  N (32, bfd_mach_riscv32, "riscv:rv32", false, NN (I_riscv32)),
-  N (32, bfd_mach_riscv32_sfpu_blackhole, "riscv:rv32-sfpu-blackhole", false, NN (I_riscv32_sfpu_blackhole)),
-  N (32, bfd_mach_riscv32_sfpu_wormhole, "riscv:rv32-sfpu-wormhole", false, NN (I_riscv32_sfpu_wormhole)),
-  N (32, bfd_mach_riscv32_sfpu, "riscv:rv32-sfpu", false, NULL)
+  N (32, bfd_mach_riscv32, "riscv:rv32", false, NULL),
 };
 
 /* The default architecture is riscv:rv64.  */

bfd/elf.c

@@ -6542,17 +6542,7 @@ _bfd_elf_init_file_header (bfd *abfd,
 	 Such need can generally be supplied by replacing the tests for
 	 e_machine with the conditions used to determine it.  */
     default:
-      if (abfd->tdata.elf_obj_data->elf_header->e_machine)
-	i_ehdrp->e_machine = abfd->tdata.elf_obj_data->elf_header->e_machine;
-      else {
-        if (riscv_machine_target != -1 &&
-              (riscv_machine_target == EM_RISCV_GRAYSKULL || riscv_machine_target == EM_RISCV_WORMHOLE 
-	       || riscv_machine_target == EM_RISCV_BLACKHOLE)) {
-	  i_ehdrp->e_machine = riscv_machine_target;
-        } else { 
-	  i_ehdrp->e_machine = bed->elf_machine_code;
-        }
-      }
+      i_ehdrp->e_machine = bed->elf_machine_code;
     }
 
   i_ehdrp->e_version = bed->s->ev_current;

bfd/elfnn-riscv.c

@@ -58,9 +58,6 @@
 #define ELF_ARCH			bfd_arch_riscv
 #define ELF_TARGET_ID			RISCV_ELF_DATA
 #define ELF_MACHINE_CODE		EM_RISCV
-#define ELF_MACHINE_ALT1    		EM_RISCV_GRAYSKULL
-#define ELF_MACHINE_ALT2    		EM_RISCV_WORMHOLE
-#define ELF_MACHINE_ALT3                EM_RISCV_BLACKHOLE
 #define ELF_MAXPAGESIZE			0x1000
 #define ELF_COMMONPAGESIZE		0x1000
 

bfd/elfxx-riscv.c

@@ -1249,24 +1249,9 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
 
 static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
 {
-  {NULL, 0, 0, 0, 0}
-};
-
-static struct riscv_supported_ext riscv_supported_sfpu_y_ext[] =
-{
-  {"y", ISA_SPEC_CLASS_SFPU, 1, 0, 0},
-  {NULL, 0, 0, 0, 0}
-};
-
-static struct riscv_supported_ext riscv_supported_sfpu_w_ext[] =
-{
-  {"w", ISA_SPEC_CLASS_SFPU_WORMHOLE, 1, 0, 0},
-  {NULL, 0, 0, 0, 0}
-};
-
-static struct riscv_supported_ext riscv_supported_sfpu_l_ext[] =
-{
-  {"l", ISA_SPEC_CLASS_SFPU_BLACKHOLE, 1, 0, 0},
+  {"xttgs",       ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
+  {"xttwh",       ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
+  {"xttbh",       ISA_SPEC_CLASS_DRAFT,   1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
 
@@ -1277,9 +1262,6 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
   riscv_supported_std_s_ext,
   riscv_supported_std_zxm_ext,
   riscv_supported_vendor_x_ext,
-  riscv_supported_sfpu_y_ext,
-  riscv_supported_sfpu_w_ext,
-  riscv_supported_sfpu_l_ext,
   NULL
 };
 
@@ -1290,9 +1272,6 @@ enum riscv_prefix_ext_class
   RV_ISA_CLASS_S,
   RV_ISA_CLASS_ZXM,
   RV_ISA_CLASS_X,
-  RV_ISA_CLASS_SFPU,
-  RV_ISA_CLASS_SFPU_WORMHOLE,
-  RV_ISA_CLASS_SFPU_BLACKHOLE,
   RV_ISA_CLASS_UNKNOWN
 };
 
@@ -1314,9 +1293,6 @@ static const struct riscv_parse_prefix_config parse_config[] =
   {RV_ISA_CLASS_Z, "z"},
   {RV_ISA_CLASS_S, "s"},
   {RV_ISA_CLASS_X, "x"},
-  {RV_ISA_CLASS_SFPU, "y"},
-  {RV_ISA_CLASS_SFPU_WORMHOLE, "w"},
-  {RV_ISA_CLASS_SFPU_BLACKHOLE, "l"},
   {RV_ISA_CLASS_UNKNOWN, NULL}
 };
 
@@ -1370,12 +1346,6 @@ riscv_recognized_prefixed_ext (const char *ext)
     if (strcmp (ext, "x") != 0)
       return true;
     break;
-  case RV_ISA_CLASS_SFPU:
-    return riscv_known_prefixed_ext (ext, riscv_supported_sfpu_y_ext);
-  case RV_ISA_CLASS_SFPU_WORMHOLE:
-    return riscv_known_prefixed_ext (ext, riscv_supported_sfpu_w_ext);
-  case RV_ISA_CLASS_SFPU_BLACKHOLE:
-    return riscv_known_prefixed_ext (ext, riscv_supported_sfpu_l_ext);
   default:
     break;
   }
@@ -1549,9 +1519,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
     case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
     case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
     case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
-    case RV_ISA_CLASS_SFPU: table = riscv_supported_sfpu_y_ext; break;
-    case RV_ISA_CLASS_SFPU_WORMHOLE: table = riscv_supported_sfpu_w_ext; break;
-    case RV_ISA_CLASS_SFPU_BLACKHOLE: table = riscv_supported_sfpu_l_ext; break;
+
     default:
       table = riscv_supported_std_ext;
     }
@@ -1571,16 +1539,6 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
     }
 }
 
-bool
-riscv_ext_dont_care_version (const char *subset)
-{
-  if (strcmp (subset, "y") == 0
-      || strcmp (subset, "w") == 0
-      || strcmp (subset, "l") == 0)
-    return true;
-  return false;
-}
-
 /* Find the default versions for the extension before adding them to
    the subset list, if their versions are RISCV_UNKNOWN_VERSION.
    Afterwards, report errors if we can not find their default versions.  */
@@ -1600,13 +1558,6 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
     riscv_get_default_ext_version (rps->isa_spec, subset,
 				   &major_version, &minor_version);
 
-  if (riscv_ext_dont_care_version (subset))
-    {
-      riscv_add_subset (rps->subset_list, subset,
-			major_version, minor_version);
-      return;
-    }
-
   /* We don't care the versions of the implicit extensions.  */
   if (!implicit
       && (major_version == RISCV_UNKNOWN_VERSION
@@ -1618,10 +1569,7 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
 	   subset);
       /* Allow old ISA spec can recognize zicsr and zifencei.  */
       else if (strcmp (subset, "zicsr") != 0
-	       && strcmp (subset, "zifencei") != 0
-               && strcmp (subset, "iy") != 0
-               && strcmp (subset, "iw") != 0
-               && strcmp (subset, "il") != 0)
+	       && strcmp (subset, "zifencei") != 0)
 	rps->error_handler
 	  (_("cannot find default versions of the ISA extension `%s'"),
 	   subset);
@@ -2464,12 +2412,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
       return riscv_subset_supports (rps, "h");
-    case INSN_CLASS_I_Y:
-      return riscv_subset_supports (rps, "y");
-    case INSN_CLASS_I_W:
-      return riscv_subset_supports (rps, "w");
-    case INSN_CLASS_I_L:
-      return riscv_subset_supports (rps, "l");
+    case INSN_CLASS_XTTGS:
+      return riscv_subset_supports (rps, "xttgs");
+    case INSN_CLASS_XTTWH:
+      return riscv_subset_supports (rps, "xttwh");
+    case INSN_CLASS_XTTBH:
+      return riscv_subset_supports (rps, "xttbh");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
@@ -2595,12 +2543,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "svinval";
     case INSN_CLASS_H:
       return _("h");
-    case INSN_CLASS_I_Y:
-      return "y";
-    case INSN_CLASS_I_W:
-      return "w";
-    case INSN_CLASS_I_L:
-      return "l";
+    case INSN_CLASS_XTTGS:
+      return "xttgs";
+    case INSN_CLASS_XTTWH:
+      return "xttwh";
+    case INSN_CLASS_XTTBH:
+      return "xttbh";
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));

bfd/format.c

@@ -279,71 +279,6 @@ bfd_check_format_matches (bfd *abfd, bfd_format format, char ***matching)
 
       cleanup = BFD_SEND_FMT (abfd, _bfd_check_format, (abfd));
 
-      // FIXME: The handling of rhese variants as new machine types is
-      // wrong. We should be using the _X<name> extension mechanism
-
-      // check if input object file machine code is WORMHOLE, GRAYSKULL, BLACKHOLE.
-      if (abfd->tdata.elf_obj_data && abfd->tdata.elf_obj_data->elf_header
-	  && abfd->tdata.elf_obj_data->elf_header->e_machine != riscv_machine_target) {
-        if ((riscv_machine_target == -1
-	     || riscv_machine_target == EM_RISCV) && // Allow plain RISCV to decay to TT cpu
-            (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_GRAYSKULL ||
-             abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_WORMHOLE || 
-             abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_BLACKHOLE ||
-             abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV )) {
-          riscv_machine_target = abfd->tdata.elf_obj_data->elf_header->e_machine;
-	} else if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV
-		   && (riscv_machine_target == EM_RISCV_GRAYSKULL
-		       || riscv_machine_target == EM_RISCV_WORMHOLE
-		       || riscv_machine_target == EM_RISCV_BLACKHOLE))
-	  ; // Allow RISCV to keep
-        else if (riscv_machine_target == EM_RISCV_GRAYSKULL) {
-          if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_WORMHOLE) {
-            _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is grayskull "
-                        	"but got wormhole object file"), abfd);
-                       		xexit (0);
-          } else if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_BLACKHOLE) {
-            _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is grayskull "
-                        	"but got blackhole object file"), abfd);
-                        	xexit (0);
-          }       
-        } else if (riscv_machine_target == EM_RISCV_WORMHOLE) {
-          if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_GRAYSKULL) {
-            _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is wormhole "
-                        	"but got grayskull object file"), abfd);
-                       		xexit (0);
-          } else if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_BLACKHOLE) {
-            _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is wormhole "
-                        	"but got blackhole object file"), abfd);
-                       		 xexit (0);
-          }       
-        } else if (riscv_machine_target == EM_RISCV_BLACKHOLE) {
-          if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_GRAYSKULL) {
-            _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is blackhole "
-                        	"but got grayskull object file"), abfd);
-                        	xexit (0);
-          } else if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_WORMHOLE) {
-            _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is blackhole "
-                        	"but got wormhole object file"), abfd);
-                        	xexit (0);
-          }
-        } else if (riscv_machine_target == EM_RISCV) {
-	  if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_GRAYSKULL) {
-	      _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is riscv "
-				   "but got grayskull object file"), abfd);
-				   xexit (0);
-	  } else if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_WORMHOLE) {
-	      _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is riscv "
-				   "but got wormhole object file"), abfd);
-				   xexit (0);
-	  } else if (abfd->tdata.elf_obj_data->elf_header->e_machine == EM_RISCV_BLACKHOLE) {
-	      _bfd_error_handler(_("%pB: Incorrect machine target. \nCurrent machine target is riscv "
-				   "but got blackhole object file"), abfd);
-				   xexit (0);
-	  }
-	}
-      }
-
       if (cleanup)
 	goto ok_ret;
 

binutils/dwarf.c

@@ -8707,7 +8707,6 @@ init_dwarf_regnames_by_elf_machine_code (unsigned int e_machine)
       break;
 
     case EM_RISCV:
-    case EM_RISCV_GRAYSKULL: case EM_RISCV_WORMHOLE: case EM_RISCV_BLACKHOLE:
       init_dwarf_regnames_riscv ();
       break;