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| 1 | +/** @file |
| 2 | +Support for the PCI Express 7.0 standard. |
| 3 | +
|
| 4 | +This header file may not define all structures. Please extend as required. |
| 5 | +
|
| 6 | +Copyright (c) 2025, American Megatrends International LLC. All rights reserved.<BR> |
| 7 | +SPDX-License-Identifier: BSD-2-Clause-Patent |
| 8 | +
|
| 9 | +**/ |
| 10 | + |
| 11 | +#ifndef PCIEXPRESS70_H_ |
| 12 | +#define PCIEXPRESS70_H_ |
| 13 | + |
| 14 | +#include <IndustryStandard/PciExpress60.h> |
| 15 | + |
| 16 | +/// The Physical Layer PCI Express Extended Capability definitions. |
| 17 | +/// |
| 18 | +/// Based on section 7.7.8 of PCI Express Base Specification 7.0 |
| 19 | +///@{ |
| 20 | +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_128_0_ID 0x0039 |
| 21 | +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_128_0_VER1 0x1 |
| 22 | + |
| 23 | +// Register offsets from Physical Layer PCI-E Ext Cap Header |
| 24 | +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_CAPABILITIES_OFFSET 0x04 |
| 25 | +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_CONTROL_OFFSET 0x08 |
| 26 | +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_STATUS_OFFSET 0x0C |
| 27 | +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10 |
| 28 | + |
| 29 | +#pragma pack(1) |
| 30 | + |
| 31 | +typedef union { |
| 32 | + struct { |
| 33 | + UINT32 SupportedLinkSpeedsVector2 : 8; // bits 0..7 |
| 34 | + UINT32 LowerSkpOsGenLnkSpeedsVect2 : 8; // bits 8..15 |
| 35 | + UINT32 LowerSkpOsRecLnkSpeedsVect2 : 8; // bits 16..23 |
| 36 | + UINT32 Reserved : 8; // bits 24..31 |
| 37 | + } Bits; |
| 38 | + UINT32 Uint32; |
| 39 | +} PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_CAPABILITIES; |
| 40 | + |
| 41 | +typedef union { |
| 42 | + struct { |
| 43 | + UINT32 Reserved : 32; // Reserved bit 0:31 |
| 44 | + } Bits; |
| 45 | + UINT32 Uint32; |
| 46 | +} PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_CONTROL; |
| 47 | + |
| 48 | +typedef union { |
| 49 | + struct { |
| 50 | + UINT32 EqualizationComplete : 1; // bit 0 |
| 51 | + UINT32 EqualizationPhase1Success : 1; // bit 1 |
| 52 | + UINT32 EqualizationPhase2Success : 1; // bit 2 |
| 53 | + UINT32 EqualizationPhase3Success : 1; // bit 3 |
| 54 | + UINT32 LinkEqualizationRequest : 1; // bit 4 |
| 55 | + UINT32 TransmitterPrecodingOn : 1; // bit 5 |
| 56 | + UINT32 TransmitterPrecodeRequest : 1; // bit 6 |
| 57 | + UINT32 NoEqualizationNeededRcvd : 1; // bit 7 |
| 58 | + UINT32 Reserved : 24; // Reserved bit 8:31 |
| 59 | + } Bits; |
| 60 | + UINT32 Uint32; |
| 61 | +} PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_STATUS; |
| 62 | + |
| 63 | +typedef union { |
| 64 | + struct { |
| 65 | + UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3 |
| 66 | + UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7 |
| 67 | + } Bits; |
| 68 | + UINT8 Uint8; |
| 69 | +} PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_LANE_EQUALIZATION_CONTROL; |
| 70 | + |
| 71 | +typedef struct { |
| 72 | + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; |
| 73 | + PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_CAPABILITIES Capablities; |
| 74 | + PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_CONTROL Control; |
| 75 | + PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_STATUS Status; |
| 76 | + PCI_EXPRESS_REG_PHYSICAL_LAYER_128_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1]; |
| 77 | +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_128_0; |
| 78 | +///@} |
| 79 | + |
| 80 | +#pragma pack() |
| 81 | + |
| 82 | +#endif |
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