From 87b76cadd71c8b191b2a5557ea77f844d2b7c1be Mon Sep 17 00:00:00 2001 From: Pranav Rama Date: Fri, 1 May 2020 18:07:38 -0500 Subject: [PATCH] first clean pass --- src/peripherals_tm4c/adc.rs | 110 ++++------- src/peripherals_tm4c/gpio.rs | 357 ++++++++--------------------------- 2 files changed, 122 insertions(+), 345 deletions(-) diff --git a/src/peripherals_tm4c/adc.rs b/src/peripherals_tm4c/adc.rs index 6dd72ce..6b631bb 100644 --- a/src/peripherals_tm4c/adc.rs +++ b/src/peripherals_tm4c/adc.rs @@ -3,24 +3,11 @@ use lc3_traits::peripherals::adc::{ AdcStateMismatch as StateMismatch, }; extern crate tm4c123x; -use tm4c123x_hal::{Peripherals, prelude::*}; -use tm4c123x::adc0; +use tm4c123x_hal::prelude::*; use tm4c123x_hal::sysctl; - // ADC0_PC_R &= ~0xF; // 7) clear max sample rate field - // ADC0_PC_R |= 0x1; // configure for 125K samples/sec - // ADC0_SSPRI_R = 0x0123; // 8) Sequencer 3 is highest priority - // ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3 - // ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger - // ADC0_SSMUX3_R &= ~0x000F; // 11) clear SS3 field - // ADC0_SSMUX3_R += 9; // set channel - // ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0 - // ADC0_IM_R &= ~0x0008; // 13) disable SS3 interrupts - // ADC0_ACTSS_R |= 0x0008; // 14) enable sample sequencer 3 - pub struct AdcShim { states: PinArr, - //components: Option, } #[derive(Copy, Clone, Debug, PartialEq)] @@ -29,7 +16,7 @@ pub enum State { Disabled, } -pub struct required_components{ +pub struct RequiredComponents{ pub adc0: tm4c123x::ADC0, pub adc1: tm4c123x::ADC1, pub porte: tm4c123x::GPIO_PORTE, @@ -51,7 +38,6 @@ impl Default for AdcShim { fn default() -> Self { Self { states: PinArr([State::Disabled; Pin::NUM_PINS]), - //components: None, } } } @@ -60,42 +46,32 @@ impl Default for AdcShim { pub struct SetError(StateMismatch); impl AdcShim { - pub fn new(power: &tm4c123x_hal::sysctl::PowerControl, peripheral_set: required_components) -> Self { + pub fn new(power: &tm4c123x_hal::sysctl::PowerControl, peripheral_set: RequiredComponents) -> Self { let mut ad0 = peripheral_set.adc0; let mut ad1 = peripheral_set.adc1; - //let d = peripheral_set.porte.amsel; let mut porte = peripheral_set.porte.split(power); let porte_ams = unsafe { &*tm4c123x::GPIO_PORTE::ptr() }; - porte_ams.dir.write(|w| unsafe{w.bits((porte_ams.dir.read().bits() & !0x003F ))}); - porte_ams.afsel.write(|w| unsafe{w.bits((porte_ams.afsel.read().bits() | 0x003F ))}); - porte_ams.den.write(|w| unsafe{w.bits((porte_ams.den.read().bits() & !0x003F ))}); - porte_ams.amsel.write(|w| unsafe{w.bits((porte_ams.amsel.read().bits() | 0x003F ))}); + porte_ams.dir.write(|w| unsafe{w.bits(porte_ams.dir.read().bits() & !0x003F )}); + porte_ams.afsel.write(|w| unsafe{w.bits(porte_ams.afsel.read().bits() | 0x003F )}); + porte_ams.den.write(|w| unsafe{w.bits(porte_ams.den.read().bits() & !0x003F )}); + porte_ams.amsel.write(|w| unsafe{w.bits(porte_ams.amsel.read().bits() | 0x003F )}); let p = unsafe { &*tm4c123x::SYSCTL::ptr() }; - // p.rcgcadc.write(|w| unsafe{w.bits(p.rcgcadc.read().bits() | 1)}); //activate adc0 - // for pat in 0..100 { - - // } sysctl::control_power( power, sysctl::Domain::Adc0, sysctl::RunMode::Run, sysctl::PowerState::On); sysctl::reset(power, sysctl::Domain::Adc0); ad0.sspri.write(|w| unsafe{w.bits(0x0123)}); - ad0.actss.write(|w| unsafe{w.bits((ad0.actss.read().bits() & !0x0008) )}); - ad0.emux.write(|w| unsafe{w.bits((ad0.emux.read().bits() & !0xF000) )}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 9 ))}); + ad0.actss.write(|w| unsafe{w.bits(ad0.actss.read().bits() & !0x0008)}); + ad0.emux.write(|w| unsafe{w.bits(ad0.emux.read().bits() & !0xF000)}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 9 )}); ad0.ssctl3.write(|w| unsafe{w.bits(0x06)}); - // ad0.pc.write(|w| unsafe{w.bits((ad0.pc.read().bits() & !0x0F) )}); - // ad0.pc.write(|w| unsafe{w.bits((ad0.pc.read().bits() | 0x01) )}); - // ad0.ssctl3.write(|w| unsafe{w.bits(0x06)}); - // ad0.sspri.write(|w| unsafe{w.bits(0x0123)}); - ad0.im.write(|w| unsafe{w.bits((ad0.im.read().bits() & !0x0008 ))}); + ad0.im.write(|w| unsafe{w.bits(ad0.im.read().bits() & !0x0008 )}); + Self{ states: PinArr([State::Disabled; Pin::NUM_PINS]), - //components: Some(peripheral_set), - } } @@ -119,29 +95,29 @@ impl Adc for AdcShim { let x = usize::from(pin); match x{ 0 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 0 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 0 )}); } 1 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 1 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 1 )}); } 2 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 2 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 2 )}); } 3 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 3 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 3 )}); } 4 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 8 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 8 )}); } 5 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 9 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 9 )}); } @@ -151,14 +127,13 @@ impl Adc for AdcShim { } - ad0.actss.write(|w| unsafe{w.bits((ad0.actss.read().bits() | 0x0008 ))}); + ad0.actss.write(|w| unsafe{w.bits(ad0.actss.read().bits() | 0x0008 )}); }, Disabled => { self.states[pin] = State::Disabled; - let ad0 = unsafe { &*tm4c123x::ADC0::ptr() }; - // ad0.actss.write(|w| unsafe{w.bits((ad0.actss.read().bits() & !0x0008 ))}); + let ad0 = unsafe { &*tm4c123x::ADC0::ptr() }; }, }; Ok(()) @@ -168,13 +143,6 @@ impl Adc for AdcShim { self.states[pin].into() } - // ADC0_PSSI_R = 0x0008; // 1) initiate SS3 - // while((ADC0_RIS_R&0x08)==0){}; // 2) wait for conversion done - // // if you have an A0-A3 revision number, you need to add an 8 usec wait here - // result = ADC0_SSFIFO3_R&0xFFF; // 3) read result - // ADC0_ISC_R = 0x0008; // 4) acknowledge completion - // return result; - fn read(&self, pin: Pin) -> Result { use State::*; match self.states[pin] { @@ -183,29 +151,29 @@ impl Adc for AdcShim { let x = usize::from(pin); match x{ 0 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 0 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 0 )}); } 1 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 1 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 1 )}); } 2 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 2 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 2 )}); } 3 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 3 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 3 )}); } 4 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 8 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 8 )}); } 5 => { - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))}); - ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 9 ))}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )}); + ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 9 )}); } diff --git a/src/peripherals_tm4c/gpio.rs b/src/peripherals_tm4c/gpio.rs index a9f24c8..1db10eb 100644 --- a/src/peripherals_tm4c/gpio.rs +++ b/src/peripherals_tm4c/gpio.rs @@ -1,4 +1,3 @@ -use core::marker::PhantomData; use core::ops::{Index, IndexMut}; use core::sync::atomic::{AtomicBool, Ordering}; use lc3_traits::peripherals::gpio::GpioState::Interrupt; @@ -8,11 +7,8 @@ use lc3_traits::peripherals::gpio::{ extern crate embedded_hal; extern crate tm4c123x; use tm4c123x_hal::gpio::*; -use tm4c123x_hal::gpio::{gpioa::*, gpiob::*, gpioe::*, gpiof::*}; +use tm4c123x_hal::gpio::{gpiob::*, gpiof::*}; use tm4c123x_hal::timer; -use tm4c123x_hal::{ - prelude::_embedded_hal_digital_InputPin, prelude::_embedded_hal_digital_OutputPin, -}; use tm4c123x_hal::{prelude::*, Peripherals}; extern crate cortex_m; use cortex_m::interrupt as cortex_int; @@ -21,12 +17,9 @@ use tm4c123x::NVIC as nvic; static mut GPIO_INTERRUPTS: [u8; 8] = [0; 8]; -//static mut GPIO_ATOMIC_FLAGS: Option<&GpioPinArr> = None; -//static mut GPIO_INTERRPUT_F: i32 = 0; #[derive(Copy, Clone, Debug, PartialEq)] -//static mut peripheral: tm4c123x_hal::Peripherals = Peripherals::take().unwrap(); pub enum State { Input(bool), Output(bool), @@ -34,9 +27,7 @@ pub enum State { Disabled, } -pub struct required_components { - // pub portf: tm4c123x::GPIO_PORTF, - // pub portb: tm4c123x::GPIO_PORTB, +pub struct RequiredComponents { pub pf1: PF1>, pub pf2: PF2>, pub pf4: PF4>, @@ -71,7 +62,7 @@ enum physical_pin_mappings { GPIO7(PB4>), } -pub struct mapping(pub [T; GpioPin::NUM_PINS]); +pub struct Mapping(pub [T; GpioPin::NUM_PINS]); pub enum State2 where @@ -85,106 +76,32 @@ where } pub enum PhysicalPins { - g0(State2>, PF1>>), - g1(State2>, PF2>>), - g2(State2>, PF4>>), - g3(State2>, PB0>>), - g4(State2>, PB1>>), - g5(State2>, PB2>>), - g6(State2>, PB3>>), - g7(State2>, PB4>>), + G0(State2>, PF1>>), + G1(State2>, PF2>>), + G2(State2>, PF4>>), + G3(State2>, PB0>>), + G4(State2>, PB1>>), + G5(State2>, PB2>>), + G6(State2>, PB3>>), + G7(State2>, PB4>>), } pub struct physical_pins<'a> { states: GpioPinArr, flags: Option<&'a GpioPinArr>, - //mapping: [physical_pin_mappings; 8], - mapping2: [PhysicalPins; 8], + mappinG2: [PhysicalPins; 8], Peripheral_set: Option<&'a mut tm4c123x_hal::Peripherals>, } impl Default for physical_pins<'_> { fn default() -> Self { unimplemented!() - // let mut states_init = [ - // State::Output(false), - // State::Output(false), - // State::Output(false), - // State::Output(false), - // State::Input(false), - // State::Input(false), - // State::Input(false), - // State::Input(false), - // ]; - // // let p = hal::Peripherals::take().unwrap(); - // // let mut sc = p.SYSCTL.constrain(); - // // let mut portb = p.GPIO_PORTF.split(&sc.power_control); - // // // //let timer_output_pin = portb.pb0.into_af_push_pull::(&mut portb.control); - // // // // let uart_tx_pin = portb.pb1.into_af_open_drain::(&mut portb.control); - // // let mut blue_led = portb.pf2.into_push_pull_output(); - // // blue_led.set_high(); - - // let p_st = Peripherals::take().unwrap(); - // let mut sc = p_st.SYSCTL.constrain(); - // let mut portf = p_st.GPIO_PORTF.split(&sc.power_control); - // let mut gpiof1 = portf.pf1.into_push_pull_output(); - // gpiof1.set_low(); - // let mut gpiof2 = portf.pf2.into_push_pull_output(); - // gpiof2.set_high(); - // let mut gpiof4 = portf.pf4.into_push_pull_output(); - // gpiof4.set_low(); - // // let mut gpioa3 = porta.pf4.into_push_pull_output(); - // // gpioa3.set_low(); - - // let mut portb = p_st.GPIO_PORTB.split(&sc.power_control); - // let mut gpiob0 = portb.pb0.into_push_pull_output(); - // // gpioe0.set_low(); //input - no init state - // let mut gpiob1 = portb.pb1.into_pull_up_input(); - // // gpioe1.set_low(); - // let mut gpiob2 = portb.pb2.into_pull_up_input(); - // // gpioe2.set_low(); - // let mut gpiob3 = portb.pb3.into_pull_up_input(); - - // let mut gpiob4 = portb.pb4.into_pull_up_input(); - - // Self { - // states: GpioPinArr(states_init), - // flags: None, - // //mapping: [], - // mapping2: ([ - // PhysicalPins::g0(State2::>, PF1>>::Output( - // gpiof1, - // )), - // PhysicalPins::g1(State2::>, PF2>>::Output( - // gpiof2, - // )), - // PhysicalPins::g2(State2::>, PF4>>::Output( - // gpiof4, - // )), - // PhysicalPins::g3(State2::>, PB0>>::Output( - // gpiob0, - // )), - // PhysicalPins::g4(State2::>, PB1>>::Input( - // gpiob1, - // )), - // PhysicalPins::g5(State2::>, PB2>>::Input( - // gpiob2, - // )), - // PhysicalPins::g6(State2::>, PB3>>::Input( - // gpiob3, - // )), - // PhysicalPins::g7(State2::>, PB4>>::Input( - // gpiob4, - // )), - // ]), - // Peripheral_set: None, - // } } } impl physical_pins<'_> { pub fn new<'a>( power: &tm4c123x_hal::sysctl::PowerControl, - peripheral_set: required_components, + peripheral_set: RequiredComponents, ) -> Self { let mut states_init = [ State::Output(false), @@ -203,63 +120,50 @@ impl physical_pins<'_> { let p_core = tm4c123x_hal::CorePeripherals::steal(); nvic_field = p_core.NVIC; }; - //let mut sc = sys_init(); - // let x = p_st.GPIO_PORTA; - //let mut portf = p_st.portf.split(power); let mut gpiof1 = p_st.pf1; gpiof1.set_low(); let mut gpiof2 = p_st.pf2; gpiof2.set_low(); let mut gpiof4 = p_st.pf4; gpiof4.set_low(); - // let mut gpioa3 = porta.pf4.into_push_pull_output(); - // gpioa3.set_low(); - - //let mut portb = p_st.portb.split(power); - let mut gpiob0 = p_st.pb0;//.into_push_pull_output(); - // gpioe0.set_low(); //input - no init state + let mut gpiob0 = p_st.pb0; let mut gpiob1 = p_st.pb1; - // gpioe1.set_low(); let mut gpiob2 = p_st.pb2; - // gpioe2.set_low(); let mut gpiob3 = p_st.pb3; - let mut gpiob4 = p_st.pb4; unsafe{nvic::unmask(tm4c123x::Interrupt::GPIOF);}; unsafe{nvic_field.set_priority(tm4c123x::Interrupt::GPIOF, 1);}; unsafe{nvic_field.enable(tm4c123x::Interrupt::GPIOF);}; unsafe{cortex_int::enable();}; - //let mut gpioe4 = porte.pe4; - //let r1 = gpioe4.into_pull_up_input(); - //let r2 = r1.into_push_pull_output(); + + Self { states: GpioPinArr(states_init), flags: None, - //mapping: [], - mapping2: ([ - PhysicalPins::g0(State2::>, PF1>>::Output( + mappinG2: ([ + PhysicalPins::G0(State2::>, PF1>>::Output( gpiof1, )), - PhysicalPins::g1(State2::>, PF2>>::Output( + PhysicalPins::G1(State2::>, PF2>>::Output( gpiof2, )), - PhysicalPins::g2(State2::>, PF4>>::Output( + PhysicalPins::G2(State2::>, PF4>>::Output( gpiof4, )), - PhysicalPins::g3(State2::>, PB0>>::Output( + PhysicalPins::G3(State2::>, PB0>>::Output( gpiob0, )), - PhysicalPins::g4(State2::>, PB1>>::Input( + PhysicalPins::G4(State2::>, PB1>>::Input( gpiob1, )), - PhysicalPins::g5(State2::>, PB2>>::Input( + PhysicalPins::G5(State2::>, PB2>>::Input( gpiob2, )), - PhysicalPins::g6(State2::>, PB3>>::Input( + PhysicalPins::G6(State2::>, PB3>>::Input( gpiob3, )), - PhysicalPins::g7(State2::>, PB4>>::Input( + PhysicalPins::G7(State2::>, PB4>>::Input( gpiob4, )), ]), @@ -268,14 +172,6 @@ impl physical_pins<'_> { } } -fn sys_init() -> tm4c123x_hal::sysctl::Sysctl { - let p_st = Peripherals::take().unwrap(); - let mut sc = p_st.SYSCTL.constrain(); - sc -} - -pub trait IntoInput {} - pub struct GpioShim<'a> { states: GpioPinArr, flags: GpioPinArr>, @@ -295,21 +191,8 @@ impl IndexMut for physical_pins<'_> { } } -//SOME NOTES: This current implementation approach is very verbose due to a subtle ownership issue. TODO: Wrap into a macro, or take a different approach to the ownership. -// Also VERY IMPORTANT: Make the self[pin] update and the actual physical pin update atomic. To wrap in lock. - impl physical_pins<'_> { - // pub fn new() -> Self { - // Self::default() - // } - // pub fn new_shared() -> Arc> { - // Arc::>::default() - // } - - /// Sets a pin if it's in input or interrupt mode. - /// - /// Returns `Some(())` on success and `None` on failure. pub fn set_pin(&mut self, pin: GpioPin, bit: bool) -> Option<()> { use physical_pin_mappings::*; use PhysicalPins::*; @@ -319,7 +202,7 @@ impl physical_pins<'_> { let mut handle = { unsafe { core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], core::mem::uninitialized(), ) } @@ -328,7 +211,7 @@ impl physical_pins<'_> { $resp(mut vb) => match vb { State2::Input(mut ins) => { core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Input(ins)), ); } @@ -341,14 +224,14 @@ impl physical_pins<'_> { }; }; core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Output(out)), ); } State2::Interrupt(mut ins) => { core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Interrupt(ins)), ); } @@ -377,9 +260,6 @@ impl physical_pins<'_> { } - - // else{ - match self[pin] { _ => { self[pin] = Output(bit); @@ -387,42 +267,33 @@ impl physical_pins<'_> { match x { 0 => { - set_pin!(0, g0); + set_pin!(0, G0); } 1 => { - set_pin!(1, g1); + set_pin!(1, G1); } 2 => { - set_pin!(2, g2); + set_pin!(2, G2); } 3 => { - set_pin!(3, g3); + set_pin!(3, G3); } 4 => { - set_pin!(4, g4); + set_pin!(4, G4); } 5 => { - set_pin!(5, g5); + set_pin!(5, G5); } 6 => { - set_pin!(6, g6); + set_pin!(6, G6); } 7 => { - set_pin!(7, g7); + set_pin!(7, G7); } _ => {} - // // physical_pin_mappings::GPIO0(y) => {let mut res = PF1>{_mode: PhantomData};}, }; } - // Interrupt(prev) => { - // // Rising edge! - // if bit && !prev { - // self.raise_interrupt(pin) - // } - - // // Interrupt(bit) - // } - // Input(_) | Disabled => return None, + }; if(disabled_flag == 1){ @@ -431,14 +302,11 @@ impl physical_pins<'_> { } Some(()) - // } + } fn raise_interrupt(&self, pin: GpioPin) { - // match self.flags[pin] { - // Some(flag) => flag.store(true, Ordering::SeqCst), - // None => unreachable!(), - // } + } fn update_flags(&self){ @@ -485,9 +353,6 @@ impl physical_pins<'_> { } - /// Gets the value of a pin. - /// - /// Returns `None` when the pin is disabled. pub fn get_pin(&self, pin: GpioPin) -> Option { use State::*; @@ -497,7 +362,6 @@ impl physical_pins<'_> { } } - /// Gets the state of a pin. Infallible. pub fn get_pin_state(&self, pin: GpioPin) -> GpioState { self[pin].into() } @@ -513,7 +377,7 @@ impl<'a> Gpio<'a> for physical_pins<'a> { let mut handle = { unsafe { core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], core::mem::uninitialized(), ) } @@ -525,47 +389,29 @@ impl<'a> Gpio<'a> for physical_pins<'a> { State2::Input(mut ins) => { let new_out = ins.into_pull_up_input(); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Input(new_out)), ); } State2::Output(mut out) => { let new_out = out.into_pull_up_input(); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Input(new_out)), ); } State2::Interrupt(mut ins) =>{ let new_out = ins.into_pull_up_input(); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Interrupt(new_out)), ); }, _=> {} - // } } - // // match $ret{ - // // State2::Input(mut ins) => { - // // let new_out = ins.into_pull_up_input(); - // // core::mem::replace( - // // &mut self.mapping2[1], - // // //PhysicalPins::state(State2::Input(new_out)), - // // ); - // // } - // // State2::Output(mut out) => { - // // let new_out = out.into_pull_up_input(); - // // core::mem::replace( - // // &mut self.mapping2[1], - // // // PhysicalPins::state(State2::Input(new_out)), - // // ); - // // } - // // _ => {} }, _ => {} - // } } }; @@ -578,32 +424,31 @@ impl<'a> Gpio<'a> for physical_pins<'a> { match state { Input => { self[pin] = State::Input(false); - //self[pin]=State::Output(false); let mut x = usize::from(pin); match x { 0 => { - set_state_input!(0, PhysicalPins::g0); + set_state_input!(0, PhysicalPins::G0); } 1 => { - set_state_input!(1, PhysicalPins::g1); + set_state_input!(1, PhysicalPins::G1); } 2 => { - set_state_input!(2, PhysicalPins::g2); + set_state_input!(2, PhysicalPins::G2); } 3 => { - set_state_input!(3, PhysicalPins::g3); + set_state_input!(3, PhysicalPins::G3); } 4 => { - set_state_input!(4, PhysicalPins::g4); + set_state_input!(4, PhysicalPins::G4); } 5 => { - set_state_input!(5, PhysicalPins::g5); + set_state_input!(5, PhysicalPins::G5); } 6 => { - set_state_input!(6, PhysicalPins::g6); + set_state_input!(6, PhysicalPins::G6); } 7 => { - set_state_input!(7, PhysicalPins::g7); + set_state_input!(7, PhysicalPins::G7); } _ => {} } @@ -615,7 +460,7 @@ impl<'a> Gpio<'a> for physical_pins<'a> { let mut handle = { unsafe { core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], core::mem::uninitialized(), ) } @@ -627,21 +472,21 @@ impl<'a> Gpio<'a> for physical_pins<'a> { State2::Input(mut ins) => { let new_out = ins.into_push_pull_output(); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Output(new_out)), ); } State2::Output(mut out) => { let new_out = out.into_push_pull_output(); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Output(new_out)), ); } State2::Interrupt(mut ins) =>{ let new_out = ins.into_pull_up_input(); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Interrupt(new_out)), ); @@ -650,7 +495,6 @@ impl<'a> Gpio<'a> for physical_pins<'a> { } }, _ => {} - // } } }; @@ -662,28 +506,28 @@ impl<'a> Gpio<'a> for physical_pins<'a> { let mut x = usize::from(pin); match x { 0 => { - set_state_output!(0, PhysicalPins::g0); + set_state_output!(0, PhysicalPins::G0); } 1 => { - set_state_output!(1, PhysicalPins::g1); + set_state_output!(1, PhysicalPins::G1); } 2 => { - set_state_output!(2, PhysicalPins::g2); + set_state_output!(2, PhysicalPins::G2); } 3 => { - set_state_output!(3, PhysicalPins::g3); + set_state_output!(3, PhysicalPins::G3); } 4 => { - set_state_output!(4, PhysicalPins::g4); + set_state_output!(4, PhysicalPins::G4); } 5 => { - set_state_output!(5, PhysicalPins::g5); + set_state_output!(5, PhysicalPins::G5); } 6 => { - set_state_output!(6, PhysicalPins::g6); + set_state_output!(6, PhysicalPins::G6); } 7 => { - set_state_output!(7, PhysicalPins::g7); + set_state_output!(7, PhysicalPins::G7); } _ => {} } @@ -695,7 +539,7 @@ impl<'a> Gpio<'a> for physical_pins<'a> { let mut handle = { unsafe { core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], core::mem::uninitialized(), ) } @@ -707,22 +551,21 @@ impl<'a> Gpio<'a> for physical_pins<'a> { State2::Input(mut ins) => { ins.set_interrupt_mode(tm4c123x_hal::gpio::InterruptMode::EdgeRising); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Interrupt(ins)), ); self[pin] = State::Interrupt(false); } State2::Output(mut out) => { - // out.set_interrupt_mode(tm4c123x_hal::gpio::InterruptMode::EdgeRising); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Output(out)), ); } State2::Interrupt(mut ins) =>{ ins.set_interrupt_mode(tm4c123x_hal::gpio::InterruptMode::EdgeRising); core::mem::replace( - &mut self.mapping2[pin as usize], + &mut self.mappinG2[pin as usize], $resp(State2::Interrupt(ins)), ); self[pin] = State::Interrupt(false); @@ -733,7 +576,6 @@ impl<'a> Gpio<'a> for physical_pins<'a> { } }, _ => {} - // } } }; @@ -743,28 +585,28 @@ impl<'a> Gpio<'a> for physical_pins<'a> { let mut x = usize::from(pin); match x { 0 => { - set_state_interrupt!(0, PhysicalPins::g0); + set_state_interrupt!(0, PhysicalPins::G0); } 1 => { - set_state_interrupt!(1, PhysicalPins::g1); + set_state_interrupt!(1, PhysicalPins::G1); } 2 => { - set_state_interrupt!(2, PhysicalPins::g2); + set_state_interrupt!(2, PhysicalPins::G2); } 3 => { - set_state_interrupt!(3, PhysicalPins::g3); + set_state_interrupt!(3, PhysicalPins::G3); } 4 => { - set_state_interrupt!(4, PhysicalPins::g4); + set_state_interrupt!(4, PhysicalPins::G4); } 5 => { - set_state_interrupt!(5, PhysicalPins::g5); + set_state_interrupt!(5, PhysicalPins::G5); } 6 => { - set_state_interrupt!(6, PhysicalPins::g6); + set_state_interrupt!(6, PhysicalPins::G6); } 7 => { - set_state_interrupt!(7, PhysicalPins::g7); + set_state_interrupt!(7, PhysicalPins::G7); } _ => {} } @@ -795,41 +637,23 @@ impl<'a> Gpio<'a> for physical_pins<'a> { fn write(&mut self, pin: GpioPin, bit: bool) -> Result<(), GpioWriteError> { use State::*; - - // if let Output(_) = self[pin] { - // self[pin] = Output(bit); - // Ok(()) - // } else { - // Err(GpioWriteError((pin, self[pin].into()))) - // } self.set_pin(pin, bit); Ok(()) } - // TODO: decide functionality when no previous flag registered fn register_interrupt_flags(&mut self, flags: &'a GpioPinArr) { - // unsafe{ GPIO_ATOMIC_FLAGS = Some(flags);}; + unsafe{GPIO_INTERRUPTS = [0; 8];}; self.flags = match self.flags { None => Some(flags), Some(_) => { - // warn!("re-registering interrupt flags!"); Some(flags) } } - //unsafe{GPIO_INTERRUPTS = [0; 8];}; } fn interrupt_occurred(&self, pin: GpioPin) -> bool { - // let mut res = false; - // unsafe{ - // if(GPIO_INTERRUPTS[usize::from(pin)]==1){ - // res = true - // } - // else{ - // res=false; - // } - // }; + self.update_flags(); match self.flags { Some(flag) => { @@ -838,11 +662,8 @@ impl<'a> Gpio<'a> for physical_pins<'a> { } None => unreachable!(), } - - //res } - // TODO: decide functionality when no previous flag registered fn reset_interrupt_flag(&mut self, pin: GpioPin) { match self.flags { Some(flags) => flags[pin].store(false, Ordering::SeqCst), @@ -850,10 +671,8 @@ impl<'a> Gpio<'a> for physical_pins<'a> { } unsafe{GPIO_INTERRUPTS[usize::from(pin)]=0;}; - //unsafe{GPIO_INTERRPUT_B = 0}; } - // TODO: make this default implementation? fn interrupts_enabled(&self, pin: GpioPin) -> bool { self.get_state(pin) == Interrupt } @@ -883,16 +702,8 @@ fn GPIOF(){ GPIO_INTERRUPTS[2] = 1; sc.icr.write(|w| unsafe{w.bits(0x10)}); } - // let mut p = unsafe { &*tm4c123x::PWM0::ptr() }; - // //let p = Peripherals::take().unwrap().PWM1; - // p.enable - // .write(|w| unsafe { w.bits(p.enable.read().bits() & !1 ) }); - - // p = unsafe { &*tm4c123x::PWM1::ptr() }; - // //let p = Peripherals::take().unwrap().PWM1; - // p.enable - // .write(|w| unsafe { w.bits(p.enable.read().bits() & !2 ) }); - //DEBUG + + //DEBUG // let mut p = unsafe { &*tm4c123x::GPIO_PORTF::ptr() }; // let mut bits = p.data.read().bits(); // bits ^= 0x02; @@ -906,10 +717,10 @@ fn GPIOF(){ #[interrupt] fn GPIOB(){ - // unsafe{GPIO_INTERRPUT_B = 1}; + unsafe{ let mut sc = &*tm4c123x::GPIO_PORTB::ptr(); - //sc. + let bits = sc.ris.read().bits(); let trail_zeros = bits.trailing_zeros(); @@ -935,6 +746,4 @@ fn GPIOB(){ } }; -} -// fn SysTick() { -// } +} \ No newline at end of file