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alexrpalexrp
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Merge pull request #25886 from alexrp/kvx
beginnings of KVX target support (via CBE)
2 parents 9668098 + f34b5ce commit d182c7e

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-7
lines changed

16 files changed

+776
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‎lib/compiler/aro/aro/target.zig‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
477477
.ve,
478478
.bpfel,
479479
.bpfeb,
480+
.kvx,
480481
.s390x,
481482
=> return null,
482483

@@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
551552
.nvptx64,
552553
.wasm64,
553554
.spirv64,
555+
.kvx,
554556
.loongarch64,
555557
.mips64,
556558
.mips64el,
@@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
636638
.wasm32 => "wasm32",
637639
.wasm64 => "wasm64",
638640
.ve => "ve",
639-
// Note: propeller1, kalimba and or1k are not supported in LLVM; this is the Zig arch name
641+
// Note: propeller1, kalimba, kvx, and or1k are not supported in LLVM; this is the Zig arch name
640642
.kalimba => "kalimba",
643+
.kvx => "kvx",
641644
.propeller => "propeller",
642645
.or1k => "or1k",
643646
};

‎lib/std/Target.zig‎

Lines changed: 33 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig");
710710
pub const hexagon = @import("Target/hexagon.zig");
711711
pub const hppa = @import("Target/generic.zig");
712712
pub const kalimba = @import("Target/generic.zig");
713+
pub const kvx = @import("Target/kvx.zig");
713714
pub const lanai = @import("Target/lanai.zig");
714715
pub const loongarch = @import("Target/loongarch.zig");
715716
pub const m68k = @import("Target/m68k.zig");
@@ -1035,14 +1036,15 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
10351036
.aarch64, .aarch64_be => .AARCH64,
10361037
.alpha => .ALPHA,
10371038
.amdgcn => .AMDGPU,
1038-
.arc, .arceb => .ARC_COMPACT,
1039+
.arc, .arceb => .ARC_COMPACT2,
10391040
.arm, .armeb, .thumb, .thumbeb => .ARM,
10401041
.avr => .AVR,
10411042
.bpfeb, .bpfel => .BPF,
10421043
.csky => .CSKY,
10431044
.hexagon => .QDSP6,
10441045
.hppa, .hppa64 => .PARISC,
10451046
.kalimba => .CSR_KALIMBA,
1047+
.kvx => .KVX,
10461048
.lanai => .LANAI,
10471049
.loongarch32, .loongarch64 => .LOONGARCH,
10481050
.m68k => .@"68K",
@@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
11051107
.hppa,
11061108
.hppa64,
11071109
.kalimba,
1110+
.kvx,
11081111
.lanai,
11091112
.m68k,
11101113
.microblaze,
@@ -1310,6 +1313,7 @@ pub const Cpu = struct {
13101313
hppa,
13111314
hppa64,
13121315
kalimba,
1316+
kvx,
13131317
lanai,
13141318
loongarch32,
13151319
loongarch64,
@@ -1385,6 +1389,7 @@ pub const Cpu = struct {
13851389
hexagon,
13861390
hppa,
13871391
kalimba,
1392+
kvx,
13881393
lanai,
13891394
loongarch,
13901395
m68k,
@@ -1420,6 +1425,7 @@ pub const Cpu = struct {
14201425
.hexagon => .hexagon,
14211426
.hppa, .hppa64 => .hppa,
14221427
.kalimba => .kalimba,
1428+
.kvx => .kvx,
14231429
.lanai => .lanai,
14241430
.loongarch32, .loongarch64 => .loongarch,
14251431
.m68k => .m68k,
@@ -1623,6 +1629,7 @@ pub const Cpu = struct {
16231629
.csky,
16241630
.hexagon,
16251631
.kalimba,
1632+
.kvx,
16261633
.loongarch32,
16271634
.loongarch64,
16281635
.microblazeel,
@@ -1847,6 +1854,10 @@ pub const Cpu = struct {
18471854
.hppa64_elf,
18481855
=> &.{.hppa64},
18491856

1857+
.kvx_lp64,
1858+
.kvx_ilp32,
1859+
=> &.{.kvx},
1860+
18501861
.lanai_sysv,
18511862
=> &.{.lanai},
18521863

@@ -1936,6 +1947,7 @@ pub const Cpu = struct {
19361947
return switch (arch) {
19371948
.amdgcn => &amdgcn.cpu.gfx600,
19381949
.avr => &avr.cpu.avr1,
1950+
.kvx => &kvx.cpu.coolidge_v1,
19391951
.loongarch32 => &loongarch.cpu.generic_la32,
19401952
.loongarch64 => &loongarch.cpu.generic_la64,
19411953
.mips, .mipsel => &mips.cpu.mips32,
@@ -1987,6 +1999,7 @@ pub const Cpu = struct {
19871999
.bpfel, .bpfeb => &bpf.cpu.v3,
19882000
.csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
19892001
.hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
2002+
.kvx => &kvx.cpu.coolidge_v2,
19902003
.lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
19912004
.loongarch64 => &loongarch.cpu.la64v1_0,
19922005
.m68k => &m68k.cpu.M68000,
@@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct {
24402453
.aarch64,
24412454
.aarch64_be,
24422455
.hexagon,
2456+
.kvx,
24432457
.m68k,
24442458
.microblaze,
24452459
.microblazeel,
@@ -2666,16 +2680,20 @@ pub const DynamicLinker = struct {
26662680
},
26672681

26682682
.netbsd => switch (cpu.arch) {
2683+
.alpha,
26692684
.arm,
26702685
.armeb,
26712686
.aarch64,
26722687
.aarch64_be,
2688+
.hppa,
26732689
.m68k,
26742690
.mips,
26752691
.mipsel,
26762692
.mips64,
26772693
.mips64el,
26782694
.powerpc,
2695+
.sh,
2696+
.sheb,
26792697
.sparc,
26802698
.sparc64,
26812699
.x86,
@@ -2685,13 +2703,17 @@ pub const DynamicLinker = struct {
26852703
},
26862704

26872705
.openbsd => switch (cpu.arch) {
2706+
.alpha,
26882707
.arm,
26892708
.aarch64,
2709+
.hppa,
26902710
.mips64,
26912711
.mips64el,
26922712
.powerpc,
26932713
.powerpc64,
26942714
.riscv64,
2715+
.sh,
2716+
.sheb,
26952717
.sparc64,
26962718
.x86,
26972719
.x86_64,
@@ -2817,6 +2839,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
28172839
.bpfeb,
28182840
.bpfel,
28192841
.hppa64,
2842+
.kvx,
28202843
.loongarch64,
28212844
.mips64,
28222845
.mips64el,
@@ -2870,6 +2893,7 @@ pub fn stackAlignment(target: *const Target) u16 {
28702893
.ve,
28712894
.wasm32,
28722895
.wasm64,
2896+
.x86_64,
28732897
=> return 16,
28742898
// Some of the following prongs should really be testing the ABI, but our current `Abi` enum
28752899
// can't handle that level of nuance yet.
@@ -2882,7 +2906,7 @@ pub fn stackAlignment(target: *const Target) u16 {
28822906
.riscv64be,
28832907
=> if (!target.cpu.has(.riscv, .e)) return 16,
28842908
.x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16,
2885-
.x86_64 => return 16,
2909+
.kvx => return 32,
28862910
else => {},
28872911
}
28882912

@@ -3375,6 +3399,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
33753399
.aarch64_be,
33763400
.alpha,
33773401
.hppa64,
3402+
.kvx,
33783403
.loongarch32,
33793404
.loongarch64,
33803405
.mips64,
@@ -3482,6 +3507,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
34823507
.aarch64_be,
34833508
.alpha,
34843509
.hppa64,
3510+
.kvx,
34853511
.loongarch32,
34863512
.loongarch64,
34873513
.mips64,
@@ -3557,6 +3583,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
35573583
.bpfel,
35583584
.bpfeb,
35593585
.hppa64,
3586+
.kvx,
35603587
.loongarch64,
35613588
.mips64,
35623589
.mips64el,
@@ -3626,6 +3653,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
36263653
.hppa => .{ .hppa_elf = .{} },
36273654
.hppa64 => .{ .hppa64_elf = .{} },
36283655
.kalimba => null,
3656+
.kvx => switch (target.abi) {
3657+
.ilp32 => .{ .kvx_ilp32 = .{} },
3658+
else => .{ .kvx_lp64 = .{} },
3659+
},
36293660
.lanai => .{ .lanai_sysv = .{} },
36303661
.loongarch64 => .{ .loongarch64_lp64 = .{} },
36313662
.loongarch32 => .{ .loongarch32_ilp32 = .{} },

‎lib/std/Target/kvx.zig‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
//! This file is auto-generated by tools/update_cpu_features.zig.
2+
3+
const std = @import("../std.zig");
4+
const CpuFeature = std.Target.Cpu.Feature;
5+
const CpuModel = std.Target.Cpu.Model;
6+
7+
pub const Feature = enum {
8+
v3_1,
9+
v3_2,
10+
v4_1,
11+
};
12+
13+
pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
14+
pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
15+
pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
16+
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
17+
18+
pub const all_features = blk: {
19+
const len = @typeInfo(Feature).@"enum".fields.len;
20+
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
21+
var result: [len]CpuFeature = undefined;
22+
result[@intFromEnum(Feature.v3_1)] = .{
23+
.llvm_name = null,
24+
.description = "Enable ISA v3.1",
25+
.dependencies = featureSet(&[_]Feature{}),
26+
};
27+
result[@intFromEnum(Feature.v3_2)] = .{
28+
.llvm_name = null,
29+
.description = "Enable ISA v3.2",
30+
.dependencies = featureSet(&[_]Feature{
31+
.v3_1,
32+
}),
33+
};
34+
result[@intFromEnum(Feature.v4_1)] = .{
35+
.llvm_name = null,
36+
.description = "Enable ISA v4.1",
37+
.dependencies = featureSet(&[_]Feature{
38+
.v3_2,
39+
}),
40+
};
41+
const ti = @typeInfo(Feature);
42+
for (&result, 0..) |*elem, i| {
43+
elem.index = i;
44+
elem.name = ti.@"enum".fields[i].name;
45+
}
46+
break :blk result;
47+
};
48+
49+
pub const cpu = struct {
50+
pub const coolidge_v1: CpuModel = .{
51+
.name = "coolidge_v1",
52+
.llvm_name = null,
53+
.features = featureSet(&[_]Feature{
54+
.v3_1,
55+
}),
56+
};
57+
pub const coolidge_v2: CpuModel = .{
58+
.name = "coolidge_v2",
59+
.llvm_name = null,
60+
.features = featureSet(&[_]Feature{
61+
.v3_2,
62+
}),
63+
};
64+
};

‎lib/std/builtin.zig‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) {
274274
/// The standard `hppa64` calling convention.
275275
hppa64_elf: CommonOptions,
276276

277+
kvx_lp64: CommonOptions,
278+
kvx_ilp32: CommonOptions,
279+
277280
/// The standard `lanai` calling convention.
278281
lanai_sysv: CommonOptions,
279282

@@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) {
959962
.csky,
960963
.hppa,
961964
.hppa64,
965+
.kvx,
962966
.lanai,
963967
.loongarch32,
964968
.loongarch64,

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