This repository contains Verilog projects for the Basys 3 board.
Currently, it includes the following implementations:
- ALU
- UART (Work in progress)
- Agustín Pallardó (@djpallax)
- Agustín Trachta (@AguTrachta)
| Name | Name | Last commit date | ||
|---|---|---|---|---|
This repository contains Verilog projects for the Basys 3 board.
Currently, it includes the following implementations: