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1. rtl-alu-pwm-fpga rtl-alu-pwm-fpga Public

   Structural VHDL system integrating an ALU and PWM generator on the DE10-Standard FPGA. Verified with ModelSim, Quartus, SignalTap, and oscilloscope. Focus on RTL integration and hardware-level test…

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2. pipelined-cpu-mips pipelined-cpu-mips Public

   5-stage pipelined MIPS CPU in VHDL with hazard detection, forwarding, and SignalTap-validated FPGA implementation on Cyclone V

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3. multicycle-cpu-architecture multicycle-cpu-architecture Public

   This project implements a multicycle RISC processor architecture using VHDL. It was developed as part of the *Advanced CPU Architecture and Hardware Accelerators Lab* course, focusing on digital sy…

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4. VLSI-Design-LABs VLSI-Design-LABs Public