XiangShan
Open-source high-performance RISC-V processor
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Repositories
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- FATE-DDR Public
FATE is a DDR PHY emulator for Xilinx FPGA platforms. It is designed to solve the frequency mismatch problem between the CPU and DDR memory in FPGA-based pre-silicon performance evaluation of processors.
- XiangShan-Dashboard Public
- XiangShanLab Public
XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.
