Issues

• Bug Report: FENCE.I hangs when the data cache has no dirty line

  RoaLogic/RV12#67 · Filter by author ororomik opened on Nov 10, 2026

• Bug Report: After an instruction fetch bus error the first instructions of the trap handler are skipped

  RoaLogic/RV12#66 · Filter by author ororomik opened on Nov 10, 2026

• Bug Report: The wrapper ties PMP_CNT to zero so the PMP CSRs do not exist when PMP_CNT is 16

  RoaLogic/RV12#65 · Filter by author ororomik opened on Nov 10, 2026

• RV32: S/U-mode XLEN becomes 0 after an M-mode mstatus write

  RoaLogic/RV12#64 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• Parcel queue shifts fetch status by 16 bits per parcel, raising a false page fault

  RoaLogic/RV12#63 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• MRET right after a faulting load corrupts mstatus.MPP

  RoaLogic/RV12#62 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• MUL/DIV behind a faulting load or store still retires

  RoaLogic/RV12#61 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• Fetch-stage exception is lost when pre-decode stalls

  RoaLogic/RV12#60 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• URET does not raise an illegal instruction exception

  RoaLogic/RV12#59 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• Instruction access fault writes the instruction bits to mtval

  RoaLogic/RV12#58 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• C.EBREAK does not raise a breakpoint exception

  RoaLogic/RV12#57 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• ECALL after a faulting load takes a second trap and overwrites mepc/mcause

  RoaLogic/RV12#56 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• A store right after a faulting load is still written to memory

  RoaLogic/RV12#55 · Filter by author CacheGuruinthemaking opened on Nov 8, 2026

• U-mode: menvcfg/menvcfgh undriven (read X); M-mode writes trap

  RoaLogic/RV12#54 · Filter by author hakunahmattatah opened on Nov 8, 2026

• medeleg[16] is writable instead of read-only zero

  RoaLogic/RV12#53 · Filter by author bobsystone-cmd opened on Sep 24, 2026

• RV12 accepts an invalid mstatus SXL/UXL combination

  RoaLogic/RV12#52 · Filter by author bobsystone-cmd opened on Sep 24, 2026

• CSRRWI with uimm=0 to a read-only CSR is not an illegal instruction

  RoaLogic/RV12#51 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• mstatus/sstatus.SUM is writable although satp.MODE is read-only 0 (no MMU)

  RoaLogic/RV12#50 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• MRET/SRET never clear mstatus.MPRV

  RoaLogic/RV12#49 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• sie write path is not masked by mideleg: S-mode can enable a non-delegated machine interrupt

  RoaLogic/RV12#48 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• mcounteren/scounteren permission check is inverted: U-mode reads the counters when they are disabled and traps when they are enabled

  RoaLogic/RV12#47 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• A fetch error on the second half of a 32-bit instruction is dropped: only parcel 0's error is exported

  RoaLogic/RV12#46 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• mstatus.MPRV is writable but never used: explicit loads/stores keep the current privilege for PMP

  RoaLogic/RV12#45 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• A CSR write commits for an instruction that is flushed by an older instruction's trap

  RoaLogic/RV12#44 · Filter by author CacheGuruinthemaking opened on Sep 19, 2026

• sie read is not masked by mideleg: non-delegated mie enable bits are visible to S-mode

  RoaLogic/RV12#43 · Filter by author CacheGuruinthemaking opened on Sep 8, 2026