drivers: spi: siwx91x: clk_div_factor can't be 0

In gspi_siwx91x_config(), clk_div_factor can't be < 1. Therefore, we can
remove the dead code.

This code has been tested with tests/drivers/spi/spi_loopback, with a PLL
clock configured to 160MHz and a bus clock to 80MHz with success. I have
not found the case where change in GSPI_CLK_CONFIG are required.

Signed-off-by: Jérôme Pouiller <[email protected]>
Upstream-status: pr <zephyrproject-rtos#100762>

Author: jerome-pouiller

drivers/spi/spi_silabs_siwx91x_gspi.c

@@ -151,11 +151,6 @@ static int gspi_siwx91x_config(const struct device *dev, const struct spi_config
 		}
 	}
 
-	if (clk_div_factor < 1) {
-		cfg->reg->GSPI_CLK_CONFIG_b.GSPI_CLK_EN = 1;
-		cfg->reg->GSPI_CLK_CONFIG_b.GSPI_CLK_SYNC = 1;
-	}
-
 	/* Set the clock divider factor */
 	cfg->reg->GSPI_CLK_DIV = clk_div_factor;