Cherry-pick upstream PRs #8
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The fallback when a XIP external flash doesn't exist assumed that main Flash starts at address 0. Adjust placement of the EXTFLASH region to take the Flash base address and load offset into account. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100816>
xg24_dk2601b and bg22_ek4108a has PWM configuration in Devicetree, but didn't enable PWM for testing. xg24_dk2601b has RGB LEDs, add aliases to enable the rgb_led sample. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100820>
Add PWM configuration on boards that have LEDs, but were missing a definition of pwm-leds. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100820>
Add ADC to supported list for testing on boards that have a zephyr,user io-channels property. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100820>
Configure ADC and DAC to use the Analog pin on the Mikrobus connector as input/output to enable ADC and DAC samples. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100820>
Declare watchdog as supported for testing. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100820>
The Counter alarm sample contains a hard-coded list of devicetree nodes to use. Since the definition of the counter node was changed on Series 2 devices in zephyrproject-rtos#97912, this sample hasn't compiled. Update the sample to select the correct devicetree node, and add representative boards to platform_allow to allow the sample to be tested on Series 2 boards. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100822>
Add overlays enabling DMA for Silabs boards to enable use of the async API on the default shell uart. Signed-off-by: Aksel Skauge Mellbye <[email protected]> Upstream-status: pr <zephyrproject-rtos#100828>
The bit_rate variable does not bring any benefit. Signed-off-by: Jérôme Pouiller <[email protected]> Upstream-status: pr <zephyrproject-rtos#100762>
In functions requiring to lock/release resources, it is less error prone to have only one exit point and user goto to manage errors. The behavior of the new code is exactly identical to the initial one. Signed-off-by: Jérôme Pouiller <[email protected]> Upstream-status: pr <zephyrproject-rtos#100762>
Until now, GSPI_DATA_SAMPLE_EDGE was enabled as soon as the user requested
> 40Mhz (even if the actual frequency was in fact 40Mhz). However, at 40MHz
and at 80MHz, use of GSPI_DATA_SAMPLE_EDGE generated read errors on the
last bit of the transaction:
Buffer contents are different:
[...],0xaa,0xaa,0xaa,0xaa,
vs:
[...],0xaa,0xaa,0xaa,0xab,
I have not found any case where GSPI_DATA_SAMPLE_EDGE is useful, so this
patch just remove this parameter.
Signed-off-by: Jérôme Pouiller <[email protected]>
Upstream-status: pr <zephyrproject-rtos#100762>
In gspi_siwx91x_config(), clk_div_factor can't be < 1. Therefore, we can remove the dead code. This code has been tested with tests/drivers/spi/spi_loopback, with a PLL clock configured to 160MHz and a bus clock to 80MHz with success. I have not found the case where change in GSPI_CLK_CONFIG are required. Signed-off-by: Jérôme Pouiller <[email protected]> Upstream-status: pr <zephyrproject-rtos#100762>
Since actual_hz is no more needed, we can simplify gspi_siwx91x_pick_lower_freq(). Signed-off-by: Jérôme Pouiller <[email protected]> Upstream-status: pr <zephyrproject-rtos#100762>
Currently, clk_div_factor is force to 1 if user request more than 110MHz. However, in this case, gspi_siwx91x_get_divider() will never return 2 or more, unless the input clock is >= 220MHz. The si91x is not designed for such high clock frequency. So, this case has never been tested. Signed-off-by: Jérôme Pouiller <[email protected]> Upstream-status: pr <zephyrproject-rtos#100762>
jhedberg
approved these changes
Dec 10, 2025
asmellby
merged commit 01f56ea
into
SiliconLabsSoftware:silabs/v2025.12
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Cherry-pick 5 pending PRs from upstream.