Issues

• CRPR: paths, memory and runtime grow faster than the design on large propagated clock networks

  The-OpenROAD-Project/OpenSTA#452 · Filter by author oharboe opened on Nov 1, 2026

• sta: write_sdc drops a rise/fall/min/max value set that matches none of its three shapes

  The-OpenROAD-Project/OpenSTA#451 · Filter by author shivarammysore opened on Oct 31, 2026

• define_scene drops every set_load read into its mode

  The-OpenROAD-Project/OpenSTA#449 · Filter by author gadfort opened on Oct 30, 2026

• sta: write_sdc crashes after deleting an instance whose pin entered a set_false_path -to through a merge

  The-OpenROAD-Project/OpenSTA#444 · Filter by author oharboe opened on Oct 22, 2026
  1

  

• replace_cell between cells with non-equivalent timing arcs drops constant-based arc disabling until Sim is reset

  Bug

  The-OpenROAD-Project/OpenSTA#440 · Filter by author minjukim55 opened on Oct 22, 2026
  

• Verilog round trip: 18 reader/writer defects found by equivalence checking, grouped by failure mode

  The-OpenROAD-Project/OpenSTA#399 · Filter by author gadfort opened on Aug 10, 2026
  1

  

• out-of-bounds std::vector<Delay> access in RequiredCmp::requiredsSave during timing-driven global placement

  The-OpenROAD-Project/OpenSTA#398 · Filter by author dnltz opened on Jul 30, 2026
  1

  

• VerilogWriter::writeAssigns() omitted assign statement when a feed-through net name matches output port name

  Feature

  The-OpenROAD-Project/OpenSTA#315 · Filter by author jhkim-pii opened on Mar 24, 2026
  2