Fixes for ttgf180 process by TheDeepestSpace · Pull Request #222 · UTOSS/risc-v

TheDeepestSpace · 2026-04-21T05:01:11Z

Related to #221

github-actions · 2026-04-21T05:17:02Z

🔧 DE1-SoC Synthesis Report Summary Diff

RV32I

Fitter Summary

@@ -1,16 +1,16 @@
-Fitter Status : Successful - Mon May 18 04:47:41 2026
+Fitter Status : Successful - Sat May 23 02:05:37 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : utoss-risc-v
 Top-level Entity Name : top
 Family : Cyclone V
 Device : 5CSEMA5F31C6
 Timing Models : Final
-Logic utilization (in ALMs) : 1,552 / 32,070 ( 5 % )
-Total registers : 1569
+Logic utilization (in ALMs) : 1,470 / 32,070 ( 5 % )
+Total registers : 1251
 Total pins : 15 / 457 ( 3 % )
 Total virtual pins : 0
-Total block memory bits : 32,768 / 4,065,280 ( < 1 % )
-Total RAM Blocks : 8 / 397 ( 2 % )
+Total block memory bits : 16,384 / 4,065,280 ( < 1 % )
+Total RAM Blocks : 4 / 397 ( 1 % )
 Total DSP Blocks : 0 / 87 ( 0 % )
 Total HSSI RX PCSs : 0
 Total HSSI PMA RX Deserializers : 0

Fitter by entity

@@ -1,32 +1,19 @@
-Compilation Hierarchy Node                        ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                                                Entity Name         Library Name
-|top                                              1552.0 (0.5)          1700.0 (0.5)                      178.5 (0.0)                                        30.5 (0.0)                        0.0 (0.0)             1840 (1)             1569 (0)                   0 (0)          32768              8      0           15    0             |top                                                                                                               top                 work
-   |memory_map:memory_map|                        10.0 (10.0)           11.8 (11.8)                       1.8 (1.8)                                          0.0 (0.0)                         0.0 (0.0)             13 (13)              13 (13)                    0 (0)          32768              8      0           0     0             |top|memory_map:memory_map                                                                                         memory_map          work
-      |altsyncram:M0_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                                                     altsyncram          work
-         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
-      |altsyncram:M0_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1                                                                     altsyncram          work
-         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
-      |altsyncram:M1_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                                                     altsyncram          work
-         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
-      |altsyncram:M1_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1                                                                     altsyncram          work
-         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
-      |altsyncram:M2_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                                                     altsyncram          work
-         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
-      |altsyncram:M2_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1                                                                     altsyncram          work
-         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
-      |altsyncram:M3_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                                                     altsyncram          work
-         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
-      |altsyncram:M3_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1                                                                     altsyncram          work
-         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
-   |utoss_riscv:core|                             1541.5 (629.2)        1687.7 (645.6)                    176.7 (30.3)                                       30.5 (14.0)                       0.0 (0.0)             1826 (749)           1556 (466)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                                              utoss_riscv         work
-      |decode_stage:u_decode_stage|               308.5 (3.3)           398.3 (3.6)                       91.6 (0.2)                                         1.7 (0.0)                         0.0 (0.0)             88 (8)               992 (0)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage                                                                  decode_stage        work
-         |Instruction_Decode:instruction_decode|  12.7 (8.3)            13.2 (8.8)                        0.5 (0.5)                                          0.0 (0.0)                         0.0 (0.0)             31 (23)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode                            Instruction_Decode  work
-            |ALUdecoder:instanceALUDec|           4.3 (4.3)             4.3 (4.3)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             8 (8)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
-         |control_fsm:u_ctrl|                     3.4 (3.4)             3.4 (3.4)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             9 (9)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|control_fsm:u_ctrl                                               control_fsm         work
-         |registerFile:RegFile|                   289.0 (289.0)         378.2 (378.2)                     90.8 (90.8)                                        1.7 (1.7)                         0.0 (0.0)             40 (40)              992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|registerFile:RegFile                                             registerFile        work
-      |execute_stage:u_execute_stage|             449.4 (95.0)          466.3 (102.1)                     28.7 (7.8)                                         11.9 (0.7)                        0.0 (0.0)             679 (178)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage                                                                execute_stage       work
-         |ALU:alu|                                354.4 (354.4)         364.2 (364.2)                     21.0 (21.0)                                        11.2 (11.2)                       0.0 (0.0)             501 (501)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage|ALU:alu                                                        ALU                 work
-      |fetch_stage:u_fetch_stage|                 72.9 (72.9)           91.5 (91.5)                       20.5 (20.5)                                        1.9 (1.9)                         0.0 (0.0)             125 (125)            97 (97)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch_stage:u_fetch_stage                                                                    fetch_stage         work
-      |hazard_unit:u_hazard_unit|                 7.1 (7.1)             8.3 (8.3)                         1.3 (1.3)                                          0.1 (0.1)                         0.0 (0.0)             15 (15)              1 (1)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|hazard_unit:u_hazard_unit                                                                    hazard_unit         work
-      |memory_stage:u_memory_stage|               12.9 (12.9)           14.2 (14.2)                       1.7 (1.7)                                          0.4 (0.4)                         0.0 (0.0)             27 (27)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|memory_stage:u_memory_stage                                                                  memory_stage        work
-      |write_back_stage:u_write_back_stage|       61.6 (60.2)           63.6 (62.1)                       2.6 (2.4)                                          0.6 (0.6)                         0.0 (0.0)             143 (141)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage                                                          write_back_stage    work
-         |MemoryLoader:memory_loader|             1.3 (1.3)             1.5 (1.5)                         0.2 (0.2)                                          0.0 (0.0)                         0.0 (0.0)             2 (2)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage|MemoryLoader:memory_loader                               MemoryLoader        work
+Compilation Hierarchy Node                     ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                    Entity Name         Library Name
+|top                                           1470.0 (0.5)          1620.5 (0.5)                      158.5 (0.0)                                        8.0 (0.0)                         0.0 (0.0)             1780 (1)             1251 (0)                   0 (0)          16384              4      0           15    0             |top                                                                                   top                 work
+   |memory_map:memory_map|                     37.6 (37.6)           40.6 (40.6)                       3.1 (3.1)                                          0.1 (0.1)                         0.0 (0.0)             66 (66)              10 (10)                    0 (0)          16384              4      0           0     0             |top|memory_map:memory_map                                                             memory_map          work
+      |altsyncram:M0_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                         altsyncram          work
+         |altsyncram_9hp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated          altsyncram_9hp1     work
+      |altsyncram:M1_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                         altsyncram          work
+         |altsyncram_ahp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated          altsyncram_ahp1     work
+      |altsyncram:M2_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                         altsyncram          work
+         |altsyncram_bhp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated          altsyncram_bhp1     work
+      |altsyncram:M3_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                         altsyncram          work
+         |altsyncram_chp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated          altsyncram_chp1     work
+   |utoss_riscv:core|                          1431.9 (193.4)        1579.4 (208.6)                    155.4 (18.4)                                       7.9 (3.1)                         0.0 (0.0)             1713 (243)           1241 (168)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                  utoss_riscv         work
+      |ALU:alu|                                358.5 (358.5)         367.9 (367.9)                     11.8 (11.8)                                        2.4 (2.4)                         0.0 (0.0)             495 (495)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ALU:alu                                                          ALU                 work
+      |ControlFSM:control_fsm|                 28.3 (28.3)           29.3 (29.3)                       1.0 (1.0)                                          0.0 (0.0)                         0.0 (0.0)             45 (45)              17 (17)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ControlFSM:control_fsm                                           ControlFSM          work
+      |Instruction_Decode:instruction_decode|  51.3 (42.8)           52.3 (44.2)                       1.0 (1.4)                                          0.0 (0.0)                         0.0 (0.0)             96 (83)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode                            Instruction_Decode  work
+         |ALUdecoder:instanceALUDec|           8.1 (8.1)             8.1 (8.1)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             13 (13)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
+      |MemoryLoader:MemLoad|                   26.3 (26.3)           28.1 (28.1)                       1.8 (1.8)                                          0.0 (0.0)                         0.0 (0.0)             60 (60)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|MemoryLoader:MemLoad                                             MemoryLoader        work
+      |fetch:fetch|                            73.5 (73.5)           74.7 (74.7)                       1.2 (1.2)                                          0.0 (0.0)                         0.0 (0.0)             95 (95)              64 (64)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch:fetch                                                      fetch               work
+      |registerFile:RegFile|                   700.5 (700.5)         818.5 (818.5)                     120.3 (120.3)                                      2.4 (2.4)                         0.0 (0.0)             679 (679)            992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|registerFile:RegFile                                             registerFile        work

Timing

@@ -3,35 +3,35 @@
 ------------------------------------------------------------
 
 Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 2.419
+Slack : 5.124
 TNS   : 0.000
 
 Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.293
+Slack : 0.374
 TNS   : 0.000
 
 Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.868
+Slack : 8.872
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 2.786
+Slack : 5.230
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.254
+Slack : 0.387
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.826
+Slack : 8.825
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 9.385
+Slack : 11.121
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.198
+Slack : 0.180
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -39,11 +39,11 @@
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 10.432
+Slack : 11.924
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.175
+Slack : 0.171
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

RV32IB

Fitter Summary

@@ -1,16 +1,16 @@
-Fitter Status : Successful - Mon May 18 04:47:42 2026
+Fitter Status : Successful - Sat May 23 02:05:46 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : utoss-risc-v
 Top-level Entity Name : top
 Family : Cyclone V
 Device : 5CSEMA5F31C6
 Timing Models : Final
-Logic utilization (in ALMs) : 1,552 / 32,070 ( 5 % )
-Total registers : 1569
+Logic utilization (in ALMs) : 1,470 / 32,070 ( 5 % )
+Total registers : 1251
 Total pins : 15 / 457 ( 3 % )
 Total virtual pins : 0
-Total block memory bits : 32,768 / 4,065,280 ( < 1 % )
-Total RAM Blocks : 8 / 397 ( 2 % )
+Total block memory bits : 16,384 / 4,065,280 ( < 1 % )
+Total RAM Blocks : 4 / 397 ( 1 % )
 Total DSP Blocks : 0 / 87 ( 0 % )
 Total HSSI RX PCSs : 0
 Total HSSI PMA RX Deserializers : 0

Fitter by entity

@@ -1,32 +1,19 @@
-Compilation Hierarchy Node                        ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                                                Entity Name         Library Name
-|top                                              1552.0 (0.5)          1700.0 (0.5)                      178.5 (0.0)                                        30.5 (0.0)                        0.0 (0.0)             1840 (1)             1569 (0)                   0 (0)          32768              8      0           15    0             |top                                                                                                               top                 work
-   |memory_map:memory_map|                        10.0 (10.0)           11.8 (11.8)                       1.8 (1.8)                                          0.0 (0.0)                         0.0 (0.0)             13 (13)              13 (13)                    0 (0)          32768              8      0           0     0             |top|memory_map:memory_map                                                                                         memory_map          work
-      |altsyncram:M0_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                                                     altsyncram          work
-         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
-      |altsyncram:M0_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1                                                                     altsyncram          work
-         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1|altsyncram_9hp1:auto_generated                                      altsyncram_9hp1     work
-      |altsyncram:M1_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                                                     altsyncram          work
-         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
-      |altsyncram:M1_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1                                                                     altsyncram          work
-         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1|altsyncram_ahp1:auto_generated                                      altsyncram_ahp1     work
-      |altsyncram:M2_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                                                     altsyncram          work
-         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
-      |altsyncram:M2_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1                                                                     altsyncram          work
-         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1|altsyncram_bhp1:auto_generated                                      altsyncram_bhp1     work
-      |altsyncram:M3_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                                                     altsyncram          work
-         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
-      |altsyncram:M3_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1                                                                     altsyncram          work
-         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1|altsyncram_chp1:auto_generated                                      altsyncram_chp1     work
-   |utoss_riscv:core|                             1541.5 (629.2)        1687.7 (645.6)                    176.7 (30.3)                                       30.5 (14.0)                       0.0 (0.0)             1826 (749)           1556 (466)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                                              utoss_riscv         work
-      |decode_stage:u_decode_stage|               308.5 (3.3)           398.3 (3.6)                       91.6 (0.2)                                         1.7 (0.0)                         0.0 (0.0)             88 (8)               992 (0)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage                                                                  decode_stage        work
-         |Instruction_Decode:instruction_decode|  12.7 (8.3)            13.2 (8.8)                        0.5 (0.5)                                          0.0 (0.0)                         0.0 (0.0)             31 (23)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode                            Instruction_Decode  work
-            |ALUdecoder:instanceALUDec|           4.3 (4.3)             4.3 (4.3)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             8 (8)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
-         |control_fsm:u_ctrl|                     3.4 (3.4)             3.4 (3.4)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             9 (9)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|control_fsm:u_ctrl                                               control_fsm         work
-         |registerFile:RegFile|                   289.0 (289.0)         378.2 (378.2)                     90.8 (90.8)                                        1.7 (1.7)                         0.0 (0.0)             40 (40)              992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|decode_stage:u_decode_stage|registerFile:RegFile                                             registerFile        work
-      |execute_stage:u_execute_stage|             449.4 (95.0)          466.3 (102.1)                     28.7 (7.8)                                         11.9 (0.7)                        0.0 (0.0)             679 (178)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage                                                                execute_stage       work
-         |ALU:alu|                                354.4 (354.4)         364.2 (364.2)                     21.0 (21.0)                                        11.2 (11.2)                       0.0 (0.0)             501 (501)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|execute_stage:u_execute_stage|ALU:alu                                                        ALU                 work
-      |fetch_stage:u_fetch_stage|                 72.9 (72.9)           91.5 (91.5)                       20.5 (20.5)                                        1.9 (1.9)                         0.0 (0.0)             125 (125)            97 (97)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch_stage:u_fetch_stage                                                                    fetch_stage         work
-      |hazard_unit:u_hazard_unit|                 7.1 (7.1)             8.3 (8.3)                         1.3 (1.3)                                          0.1 (0.1)                         0.0 (0.0)             15 (15)              1 (1)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|hazard_unit:u_hazard_unit                                                                    hazard_unit         work
-      |memory_stage:u_memory_stage|               12.9 (12.9)           14.2 (14.2)                       1.7 (1.7)                                          0.4 (0.4)                         0.0 (0.0)             27 (27)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|memory_stage:u_memory_stage                                                                  memory_stage        work
-      |write_back_stage:u_write_back_stage|       61.6 (60.2)           63.6 (62.1)                       2.6 (2.4)                                          0.6 (0.6)                         0.0 (0.0)             143 (141)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage                                                          write_back_stage    work
-         |MemoryLoader:memory_loader|             1.3 (1.3)             1.5 (1.5)                         0.2 (0.2)                                          0.0 (0.0)                         0.0 (0.0)             2 (2)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back_stage:u_write_back_stage|MemoryLoader:memory_loader                               MemoryLoader        work
+Compilation Hierarchy Node                     ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                    Entity Name         Library Name
+|top                                           1470.0 (0.5)          1620.5 (0.5)                      158.5 (0.0)                                        8.0 (0.0)                         0.0 (0.0)             1780 (1)             1251 (0)                   0 (0)          16384              4      0           15    0             |top                                                                                   top                 work
+   |memory_map:memory_map|                     37.6 (37.6)           40.6 (40.6)                       3.1 (3.1)                                          0.1 (0.1)                         0.0 (0.0)             66 (66)              10 (10)                    0 (0)          16384              4      0           0     0             |top|memory_map:memory_map                                                             memory_map          work
+      |altsyncram:M0_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                         altsyncram          work
+         |altsyncram_9hp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated          altsyncram_9hp1     work
+      |altsyncram:M1_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                         altsyncram          work
+         |altsyncram_ahp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated          altsyncram_ahp1     work
+      |altsyncram:M2_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                         altsyncram          work
+         |altsyncram_bhp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated          altsyncram_bhp1     work
+      |altsyncram:M3_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                         altsyncram          work
+         |altsyncram_chp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated          altsyncram_chp1     work
+   |utoss_riscv:core|                          1431.9 (193.4)        1579.4 (208.6)                    155.4 (18.4)                                       7.9 (3.1)                         0.0 (0.0)             1713 (243)           1241 (168)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                  utoss_riscv         work
+      |ALU:alu|                                358.5 (358.5)         367.9 (367.9)                     11.8 (11.8)                                        2.4 (2.4)                         0.0 (0.0)             495 (495)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ALU:alu                                                          ALU                 work
+      |ControlFSM:control_fsm|                 28.3 (28.3)           29.3 (29.3)                       1.0 (1.0)                                          0.0 (0.0)                         0.0 (0.0)             45 (45)              17 (17)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ControlFSM:control_fsm                                           ControlFSM          work
+      |Instruction_Decode:instruction_decode|  51.3 (42.8)           52.3 (44.2)                       1.0 (1.4)                                          0.0 (0.0)                         0.0 (0.0)             96 (83)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode                            Instruction_Decode  work
+         |ALUdecoder:instanceALUDec|           8.1 (8.1)             8.1 (8.1)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             13 (13)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
+      |MemoryLoader:MemLoad|                   26.3 (26.3)           28.1 (28.1)                       1.8 (1.8)                                          0.0 (0.0)                         0.0 (0.0)             60 (60)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|MemoryLoader:MemLoad                                             MemoryLoader        work
+      |fetch:fetch|                            73.5 (73.5)           74.7 (74.7)                       1.2 (1.2)                                          0.0 (0.0)                         0.0 (0.0)             95 (95)              64 (64)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch:fetch                                                      fetch               work
+      |registerFile:RegFile|                   700.5 (700.5)         818.5 (818.5)                     120.3 (120.3)                                      2.4 (2.4)                         0.0 (0.0)             679 (679)            992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|registerFile:RegFile                                             registerFile        work

Timing

@@ -3,35 +3,35 @@
 ------------------------------------------------------------
 
 Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 2.419
+Slack : 5.124
 TNS   : 0.000
 
 Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.293
+Slack : 0.374
 TNS   : 0.000
 
 Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.868
+Slack : 8.872
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 2.786
+Slack : 5.230
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.254
+Slack : 0.387
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.826
+Slack : 8.825
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 9.385
+Slack : 11.121
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.198
+Slack : 0.180
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -39,11 +39,11 @@
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 10.432
+Slack : 11.924
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.175
+Slack : 0.171
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'

Comparing synthesis results from main branch vs. this PR

set default for alu src's

cc469de

TheDeepestSpace self-assigned this Apr 21, 2026

TheDeepestSpace added 2 commits April 21, 2026 05:27

fix unused signals

be091ce

remove _unused signal sinks

7adc33c

TheDeepestSpace changed the base branch from main to multicycle May 23, 2026 01:27

TheDeepestSpace marked this pull request as ready for review May 23, 2026 01:27

bump ci

92d75be

TheDeepestSpace linked an issue May 23, 2026 that may be closed by this pull request

Prepare for gf180 process #221

Open

TheDeepestSpace merged commit e2bc9d7 into multicycle May 23, 2026
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Fixes for ttgf180 process#222

Fixes for ttgf180 process#222
TheDeepestSpace merged 4 commits into
multicyclefrom
boris/ttgf180-fixes

TheDeepestSpace commented Apr 21, 2026

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github-actions Bot commented Apr 21, 2026 •

edited

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TheDeepestSpace commented Apr 21, 2026

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github-actions Bot commented Apr 21, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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🔧 DE1-SoC Synthesis Report Summary Diff

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github-actions Bot commented Apr 21, 2026 •

edited

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