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fix: use --cfg docsrs for document #27

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Merged
equation314 merged 3 commits into from
Nov 24, 2025
Merged

fix: use --cfg docsrs for document #27

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cfe9614
fix: use `--cfg docsrs` for document
AsakuraMizu Nov 24, 2025
f60b829
fix: use `--cfg docsrs` for all
AsakuraMizu Nov 24, 2025
ed48373
ci: remove "--all-features" for testing
AsakuraMizu Nov 24, 2025
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4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ jobs:
- name: Unit test
if: ${{ matrix.targets == 'x86_64-unknown-linux-gnu' }}
env:
RUSTFLAGS: --cfg doc
RUSTFLAGS: --cfg docsrs
run: cargo test --target ${{ matrix.targets }} -- --nocapture

doc:
Expand All @@ -39,7 +39,7 @@ jobs:
contents: write
env:
default-branch: ${{ format('refs/heads/{0}', github.event.repository.default_branch) }}
RUSTFLAGS: --cfg doc
RUSTFLAGS: --cfg docsrs
RUSTDOCFLAGS: -Zunstable-options --enable-index-page -D rustdoc::broken_intra_doc_links -D missing-docs
steps:
- uses: actions/checkout@v4
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43 changes: 25 additions & 18 deletions Cargo.lock
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9 changes: 5 additions & 4 deletions page_table_entry/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,12 @@ arm-el2 = []
bitflags = "2.9"
memory_addr.workspace = true

[target.'cfg(any(target_arch = "aarch64", doc))'.dependencies]
[target.'cfg(any(target_arch = "aarch64", doc, docsrs))'.dependencies]
aarch64-cpu = "10.0"

[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
x86_64 = "0.15.2"
[target.'cfg(any(target_arch = "x86_64", doc, docsrs))'.dependencies]
x86_64 = { version = "0.15", default-features = false }

[package.metadata.docs.rs]
rustc-args = ["--cfg", "doc"]
rustc-args = ["--cfg", "docsrs"]
all-features = true
12 changes: 8 additions & 4 deletions page_table_entry/src/arch/mod.rs
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Original file line number Diff line number Diff line change
@@ -1,11 +1,15 @@
#[cfg(any(target_arch = "x86_64", doc))]
#[cfg(any(target_arch = "x86_64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(target_arch = "x86_64")))]
pub mod x86_64;

#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64"))))]
pub mod riscv;

#[cfg(any(target_arch = "aarch64", doc))]
#[cfg(any(target_arch = "aarch64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(target_arch = "aarch64")))]
pub mod aarch64;

#[cfg(any(target_arch = "loongarch64", doc))]
#[cfg(any(target_arch = "loongarch64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(target_arch = "loongarch64")))]
pub mod loongarch64;
12 changes: 8 additions & 4 deletions page_table_multiarch/Cargo.toml
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Expand Up @@ -22,14 +22,18 @@ memory_addr.workspace = true
page_table_entry.workspace = true
bitmaps = { version = "3.2", default-features = false, optional = true }

[target.'cfg(any(target_arch = "x86_64", doc))'.dependencies]
[target.'cfg(any(target_arch = "x86_64", doc, docsrs))'.dependencies]
x86 = "0.52"

[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))'.dependencies]
[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc, docsrs))'.dependencies]
riscv = { version = "0.14", default-features = false }

[package.metadata.docs.rs]
rustc-args = ["--cfg", "doc"]
rustc-args = ["--cfg", "docsrs"]
all-features = true

[dev-dependencies]
rand = { version = "0.9.1", default-features = false, features = ["small_rng"] }
# FIXME: use a released version when available
rand = { version = "0.10.0-rc.5", default-features = false, features = [
"small_rng",
] }
12 changes: 8 additions & 4 deletions page_table_multiarch/src/arch/mod.rs
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Original file line number Diff line number Diff line change
@@ -1,11 +1,15 @@
#[cfg(any(target_arch = "x86_64", doc))]
#[cfg(any(target_arch = "x86_64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(target_arch = "x86_64")))]
pub mod x86_64;

#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc))]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(any(target_arch = "riscv32", target_arch = "riscv64"))))]
pub mod riscv;

#[cfg(any(target_arch = "aarch64", doc))]
#[cfg(any(target_arch = "aarch64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(target_arch = "aarch64")))]
pub mod aarch64;

#[cfg(any(target_arch = "loongarch64", doc))]
#[cfg(any(target_arch = "loongarch64", doc, docsrs))]
#[cfg_attr(doc, doc(cfg(target_arch = "loongarch64")))]
pub mod loongarch64;
4 changes: 4 additions & 0 deletions page_table_multiarch/tests/alloc_tests.rs
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Expand Up @@ -91,6 +91,7 @@ fn run_test_for<M: PagingMetaData<VirtAddr = VirtAddr>, PTE: GenericPTE>() -> Pa
}

#[test]
#[cfg(any(target_arch = "x86_64", docsrs))]
fn test_dealloc_x86() -> PagingResult<()> {
run_test_for::<
page_table_multiarch::x86_64::X64PagingMetaData,
Expand All @@ -100,6 +101,7 @@ fn test_dealloc_x86() -> PagingResult<()> {
}

#[test]
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64", docsrs))]
fn test_dealloc_riscv() -> PagingResult<()> {
run_test_for::<
page_table_multiarch::riscv::Sv39MetaData<VirtAddr>,
Expand All @@ -113,6 +115,7 @@ fn test_dealloc_riscv() -> PagingResult<()> {
}

#[test]
#[cfg(any(target_arch = "aarch64", docsrs))]
fn test_dealloc_aarch64() -> PagingResult<()> {
run_test_for::<
page_table_multiarch::aarch64::A64PagingMetaData,
Expand All @@ -122,6 +125,7 @@ fn test_dealloc_aarch64() -> PagingResult<()> {
}

#[test]
#[cfg(any(target_arch = "loongarch64", docsrs))]
fn test_dealloc_loongarch64() -> PagingResult<()> {
run_test_for::<
page_table_multiarch::loongarch64::LA64MetaData,
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