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nvme: support aarch64 and riscv64 (qemu)#677

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dumsum wants to merge 5 commits intomainfrom
simon/nvme_arm_riscv
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nvme: support aarch64 and riscv64 (qemu)#677
dumsum wants to merge 5 commits intomainfrom
simon/nvme_arm_riscv

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@dumsum dumsum commented Mar 23, 2026

Mostly some build time configuration of addresses and meta.py hacking; needed to reorder things a bit.

dumsum added 4 commits March 23, 2026 15:32
Signed-off-by: dumsum <dumsum@pm.me>
Signed-off-by: dumsum <dumsum@pm.me>
Signed-off-by: dumsum <dumsum@pm.me>
Signed-off-by: dumsum <dumsum@pm.me>
@dumsum dumsum force-pushed the simon/nvme_arm_riscv branch from 11d5437 to 16ae80a Compare March 23, 2026 04:37
Signed-off-by: dumsum <dumsum@pm.me>
@dumsum dumsum force-pushed the simon/nvme_arm_riscv branch from 16ae80a to e12a826 Compare March 23, 2026 04:51
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@midnightveil midnightveil left a comment

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I think there's some bigger issues regarding how our build systems handles variants of the same board, but in lieu of more major restructurings this seems fine.

Would it be possible to make these work in our CI autotests, or is that hard?

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