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Merged
cfallin merged 1 commit into from
Jul 24, 2026
Merged

winch(aarch64): v128 shift ops #13950

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47 changes: 47 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_shl.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.shl
(v128.const i16x8 32768 1 65535 16384 2 3 4 5)
(i32.const 2)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x7c
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #2
;; ldr q0, #0x80
;; and w0, w0, #0xf
;; dup v31.8h, w0
;; sshl v0.8h, v0.8h, v31.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 7c: udf #0xc11f
;; 80: .byte 0x00, 0x80, 0x01, 0x00
;; 84: .byte 0xff, 0xff, 0x00, 0x40
;; 88: .byte 0x02, 0x00, 0x03, 0x00
;; 8c: .byte 0x04, 0x00, 0x05, 0x00
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_shr_s.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.shr_s
(v128.const i16x8 32768 1 65535 16384 2 3 4 5)
(i32.const 2)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x80
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #2
;; ldr q0, #0x90
;; and w0, w0, #0xf
;; neg x0, x0
;; dup v31.8h, w0
;; sshl v0.8h, v0.8h, v31.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 80: udf #0xc11f
;; 84: udf #0
;; 88: udf #0
;; 8c: udf #0
;; 90: .byte 0x00, 0x80, 0x01, 0x00
;; 94: .byte 0xff, 0xff, 0x00, 0x40
;; 98: .byte 0x02, 0x00, 0x03, 0x00
;; 9c: .byte 0x04, 0x00, 0x05, 0x00
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_shr_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.shr_u
(v128.const i16x8 32768 1 65535 16384 2 3 4 5)
(i32.const 2)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x80
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #2
;; ldr q0, #0x90
;; and w0, w0, #0xf
;; neg x0, x0
;; dup v31.8h, w0
;; ushl v0.8h, v0.8h, v31.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 80: udf #0xc11f
;; 84: udf #0
;; 88: udf #0
;; 8c: udf #0
;; 90: .byte 0x00, 0x80, 0x01, 0x00
;; 94: .byte 0xff, 0xff, 0x00, 0x40
;; 98: .byte 0x02, 0x00, 0x03, 0x00
;; 9c: .byte 0x04, 0x00, 0x05, 0x00
47 changes: 47 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i32x4_shl.wat
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@@ -0,0 +1,47 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i32x4.shl
(v128.const i32x4 0x80000000 1 0xFFFFFFFF 7)
(i32.const 3)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x7c
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #3
;; ldr q0, #0x80
;; and w0, w0, #0x1f
;; dup v31.4s, w0
;; sshl v0.4s, v0.4s, v31.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 7c: udf #0xc11f
;; 80: .byte 0x00, 0x00, 0x00, 0x80
;; 84: udf #1
;; 88: .byte 0xff, 0xff, 0xff, 0xff
;; 8c: udf #7
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i32x4_shr_s.wat
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@@ -0,0 +1,51 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i32x4.shr_s
(v128.const i32x4 0x80000000 1 0xFFFFFFFF 7)
(i32.const 3)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x80
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #3
;; ldr q0, #0x90
;; and w0, w0, #0x1f
;; neg x0, x0
;; dup v31.4s, w0
;; sshl v0.4s, v0.4s, v31.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 80: udf #0xc11f
;; 84: udf #0
;; 88: udf #0
;; 8c: udf #0
;; 90: .byte 0x00, 0x00, 0x00, 0x80
;; 94: udf #1
;; 98: .byte 0xff, 0xff, 0xff, 0xff
;; 9c: udf #7
51 changes: 51 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i32x4_shr_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i32x4.shr_u
(v128.const i32x4 0x80000000 1 0xFFFFFFFF 7)
(i32.const 3)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x80
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #3
;; ldr q0, #0x90
;; and w0, w0, #0x1f
;; neg x0, x0
;; dup v31.4s, w0
;; ushl v0.4s, v0.4s, v31.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 80: udf #0xc11f
;; 84: udf #0
;; 88: udf #0
;; 8c: udf #0
;; 90: .byte 0x00, 0x00, 0x00, 0x80
;; 94: udf #1
;; 98: .byte 0xff, 0xff, 0xff, 0xff
;; 9c: udf #7
47 changes: 47 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i64x2_shl.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i64x2.shl
(v128.const i64x2 0x8000000000000000 0xFFFFFFFFFFFFFFFF)
(i32.const 2)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x7c
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; mov x0, #2
;; ldr q0, #0x80
;; and w0, w0, #0x3f
;; dup v31.2d, x0
;; sshl v0.2d, v0.2d, v31.2d
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q0, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 7c: udf #0xc11f
;; 80: udf #0
;; 84: .byte 0x00, 0x00, 0x00, 0x80
;; 88: .byte 0xff, 0xff, 0xff, 0xff
;; 8c: .byte 0xff, 0xff, 0xff, 0xff
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