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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

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  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

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  4. riscv-dv riscv-dv Public

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

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  6. firrtl firrtl Public archive

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Repositories

Showing 10 of 122 repositories
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw's past year of commit activity
    Rust 171 Apache-2.0 130 238 (8 issues need help) 82 Updated Sep 30, 2026
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl's past year of commit activity
    SystemVerilog 155 Apache-2.0 108 118 (2 issues need help) 37 Updated Sep 30, 2026
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw's past year of commit activity
    Rust 41 Apache-2.0 89 158 (5 issues need help) 100 Updated Sep 30, 2026
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2's past year of commit activity
    SystemVerilog 345 Apache-2.0 113 41 13 Updated Sep 30, 2026
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss's past year of commit activity
    SystemVerilog 53 Apache-2.0 63 96 37 Updated Sep 30, 2026
  • usb2 Public

    USB core

    chipsalliance/usb2's past year of commit activity
    VHDL 1 Apache-2.0 6 20 2 Updated Sep 30, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator's past year of commit activity
    SystemVerilog 45 935 0 0 Updated Sep 29, 2026
  • mjolnir Public

    Mjolnir: AI Vulnerability Scanning Infrastructure

    chipsalliance/mjolnir's past year of commit activity
    Python 7 Apache-2.0 6 14 1 Updated Sep 29, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests's past year of commit activity
    SystemVerilog 397 ISC 104 48 (4 issues need help) 38 Updated Sep 30, 2026
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog's past year of commit activity
    C++ 475 Apache-2.0 91 47 (2 issues need help) 0 Updated Sep 29, 2026
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