Request WG Review: Lint Error Waiver for Caliptra-ss

[tsai95]

Hi Caliptra team,

We have run the lint checks on Caliptra-SS and encountered several lint errors that require your review.
Could you please confirm if these errors can be waived?

  -----------------------------------------------------------------------------
  STARC05-1.3.1.3  (4 errors)
  -----------------------------------------------------------------------------
  Tag                 : STARC05-1.3.1.3
  Description         : Asynchronous [SetOrReset] signal '[SeqSetRstNet]' ([FlopOrLatch]: '[DesignSeqNet]') used as non-[SetOrReset]/synchronous-[SetOrReset] at instance '[DesignInstanceName]' 
  Statement           :       if (rst_l == 0)
  SetOrReset          : reset
  FlopOrLatch         : flop
  SeqSetRstNet        : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/rvtop/veer/core_rst_l
  DesignSeqNet        : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/rvtop/veer/dbg/dmstatus_haveresetn_reg/genblock.dffs/dout[0]
  DesignInstanceName  : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/rvtop/veer/dbg/rstl_syncff/u_cptra_rvsyncss_bus/genblk1[0].sync_i/genblk1.sync_hardendflop_ff_all/sync_hardendflop_ff_all/D
  Module              : el2_veer
  -----------------------------------------------------------------------------
  Tag                 : STARC05-1.3.1.3
  Description         : Asynchronous [SetOrReset] signal '[SeqSetRstNet]' ([FlopOrLatch]: '[DesignSeqNet]') used as non-[SetOrReset]/synchronous-[SetOrReset] at instance '[DesignInstanceName]' (File Name: '[RTL_FILENAME]' ,Line no.: '[RTL_LINE_NUM]')
  Statement           :     if (~hreset_n) begin
  SetOrReset          : reset
  FlopOrLatch         : flop
  SeqSetRstNet        : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/soc_ifc_top1/i_soc_ifc_boot_fsm/cptra_uc_rst_b
  DesignSeqNet        : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/u_ahb_lite_2to1_mux/initiator0_data_ph_nq
  DesignInstanceName  : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/rvtop/veer/dbg/rstl_syncff/u_cptra_rvsyncss_bus/genblk1[0].sync_i/genblk1.sync_hardendflop_ff_all/sync_hardendflop_ff_all/D
  Module              : soc_ifc_boot_fsm
  -----------------------------------------------------------------------------
  Tag                 : STARC05-1.3.1.3
  Description         : Asynchronous [SetOrReset] signal '[SeqSetRstNet]' ([FlopOrLatch]: '[DesignSeqNet]') used as non-[SetOrReset]/synchronous-[SetOrReset] at instance '[DesignInstanceName]' (File Name: '[RTL_FILENAME]' ,Line no.: '[RTL_LINE_NUM]')
  Statement           :     if (!cptra_rst_b) begin 
  SetOrReset          : reset
  FlopOrLatch         : flop
  SeqSetRstNet        : u_caliptra_ss_wrap/u_css_top/mci_top_i/i_boot_seqr/cptra_rst_b
  DesignSeqNet        : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/s_axi_active[0]
  DesignInstanceName  : u_caliptra_ss_wrap/u_css_top/caliptra_top_dut/rvtop/veer/dbg/rstl_syncff/u_cptra_rvsyncss_bus/genblk1[0].sync_i/genblk1.sync_hardendflop_ff_all/sync_hardendflop_ff_all/D
  Module              : mci_boot_seqr
  -----------------------------------------------------------------------------
  Tag                 : STARC05-1.3.1.3
  Description         : Asynchronous [SetOrReset] signal '[SeqSetRstNet]' ([FlopOrLatch]: '[DesignSeqNet]') used as non-[SetOrReset]/synchronous-[SetOrReset] at instance '[DesignInstanceName]' (File Name: '[RTL_FILENAME]' ,Line no.: '[RTL_LINE_NUM]')
  Statement           :       if (rst_l == 0)
  SetOrReset          : reset
  FlopOrLatch         : flop
  SeqSetRstNet        : u_caliptra_ss_wrap/u_css_top/rvtop_wrapper/rvtop/veer/core_rst_l
  DesignSeqNet        : u_caliptra_ss_wrap/u_css_top/rvtop_wrapper/rvtop/veer/dbg/dmstatus_haveresetn_reg/genblock.dffs/dout[0]
  DesignInstanceName  : u_caliptra_ss_wrap/u_css_top/rvtop_wrapper/rvtop/veer/dbg/rstl_syncff/u_cptra_mcu0_rvsyncss_bus/genblk1[0].sync_i/genblk1.sync_hardendflop_ff_all/sync_hardendflop_ff_all/D
  Module              : css_mcu0_el2_veer

  -----------------------------------------------------------------------------
  W156  (1 error)
  -----------------------------------------------------------------------------
  Tag           : W156
  Description   : Bus net '[Signal]' is connected in reverse.[Hierarchy: '[HIERARCHY]']
  Module        : sha512_acc_top
  LineNumber    : 145
  Statement     :                    .block_msg(block_reg),
  Signal        : block_msg
  HIERARCHY     : :u_css_top@caliptra_ss_top:caliptra_top_dut@caliptra_top:soc_ifc_top1@soc_ifc_top:i_sha512_acc_top@sha512_acc_top

  -----------------------------------------------------------------------------
  W443  (1 error)
  -----------------------------------------------------------------------------
  Tag           : W443
  Description   : Based number [VariableName] contains an X - has no meaning in synthesis
  FileName      : /caliptra_ss/src/mci/rtl/mci_pkg.sv
  LineNumber    : 48
  Statement     :         BOOT_UNKNOWN            = 'x
  VariableName  : 'bxxxx

Thank you for your review and guidance!

Tsai

[nelson-ou]

Hi Caliptra Team
Please help with review of these violation messages.
Although it was run with a different set of policies, please help clarify if these violations can be waived?
Thank you!

[clayton8]

Hi we are reviewing these violations and will get back to you shortly.