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Merged
tingleby merged 4 commits into from
Jul 11, 2024
Merged

Pwm issue #1129

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3b774c9
platform: adjusting the order of pwm pins of radxa borads
nascs Mar 26, 2024
fc20928
platform: fix the pwm function of radxa boards
nascs Mar 26, 2024
b3554c4
radxa cm5 io: remove useless pwm pins
nascs Mar 28, 2024
7fcd62e
platform: fix pwm initialization of radxa boards
nascs Mar 26, 2024
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2 changes: 1 addition & 1 deletion include/arm/radxa_rock_3c.h
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Expand Up @@ -17,7 +17,7 @@ extern "C" {
#define MRAA_RADXA_ROCK_3C_I2C_COUNT 2
#define MRAA_RADXA_ROCK_3C_SPI_COUNT 1
#define MRAA_RADXA_ROCK_3C_UART_COUNT 5
#define MRAA_RADXA_ROCK_3C_PWM_COUNT 7
#define MRAA_RADXA_ROCK_3C_PWM_COUNT 6
#define MRAA_RADXA_ROCK_3C_AIO_COUNT 0
#define MRAA_RADXA_ROCK_3C_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_ROCK_3C "Radxa ROCK3 Model C"
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2 changes: 1 addition & 1 deletion include/arm/radxa_rock_5b.h
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Expand Up @@ -17,7 +17,7 @@ extern "C" {
#define MRAA_RADXA_ROCK_5B_I2C_COUNT 4
#define MRAA_RADXA_ROCK_5B_SPI_COUNT 2
#define MRAA_RADXA_ROCK_5B_UART_COUNT 4
#define MRAA_RADXA_ROCK_5B_PWM_COUNT 10
#define MRAA_RADXA_ROCK_5B_PWM_COUNT 14
#define MRAA_RADXA_ROCK_5B_AIO_COUNT 1
#define MRAA_RADXA_ROCK_5B_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_ROCK_5B "Radxa ROCK 5B"
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29 changes: 19 additions & 10 deletions src/arm/radxa_cm3.c
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Expand Up @@ -96,24 +96,33 @@ mraa_radxa_cm3()
return NULL;
}

b->pins[13].pwm.parent_id = 0; // pwm0-m0
b->pins[13].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 0; // pwm0-m1
b->pins[11].pwm.mux_total = 0;
b->pins[5].pwm.parent_id = 1; // pwm1-m1
b->pins[5].pwm.mux_total = 0;
b->pins[3].pwm.parent_id = 2; // pwm2-m1
b->pins[3].pwm.mux_total = 0;
b->pins[37].pwm.parent_id = 3; // pwm3
b->pins[37].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[5].pwm.parent_id = 1; // pwm1-m1
b->pins[5].pwm.mux_total = 0;
b->pins[5].pwm.pinmap = 0;
b->pins[11].pwm.parent_id = 0; // pwm0-m1
b->pins[11].pwm.mux_total = 0;
b->pins[11].pwm.pinmap = 0;
b->pins[13].pwm.parent_id = 0; // pwm0-m0
b->pins[13].pwm.mux_total = 0;
b->pins[13].pwm.pinmap = 0;
b->pins[15].pwm.parent_id = 4; // pwm4
b->pins[15].pwm.mux_total = 0;
b->pins[15].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 6; // pwm6
b->pins[31].pwm.mux_total = 0;
b->pins[33].pwm.parent_id = 15; // pwm7
b->pins[33].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 11; // pwm11-m1
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[33].pwm.parent_id = 7; // pwm7
b->pins[33].pwm.mux_total = 0;
b->pins[33].pwm.pinmap = 0;
b->pins[37].pwm.parent_id = 3; // pwm3
b->pins[37].pwm.mux_total = 0;
b->pins[37].pwm.pinmap = 0;

mraa_radxa_cm3_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_cm3_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3.3V");
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28 changes: 14 additions & 14 deletions src/arm/radxa_cm5_io.c
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Expand Up @@ -90,27 +90,27 @@ mraa_radxa_cm5_io()
return NULL;
}

b->pins[38].pwm.parent_id = 0; // PWM0-M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 6; // PWM6-M0
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[3].pwm.parent_id = 10; // PWM10-M2
b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 14; // PWM14-M1
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 7; // PWM7-M0
b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0;
b->pins[16].pwm.parent_id = 11; // PWM11-M0
b->pins[16].pwm.mux_total = 0;
b->pins[16].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 6; // PWM6-M0
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 13; // PWM13-M2
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 11; // PWM14-M1
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;
b->pins[36].pwm.parent_id = 15; // PWM15-M2
b->pins[36].pwm.mux_total = 0;
b->pins[36].pwm.pinmap = 0;
b->pins[38].pwm.parent_id = 0; // PWM0-M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;

// AIO
b->aio_count = MRAA_RADXA_CM5_IO_AIO_COUNT;
Expand All @@ -123,7 +123,7 @@ mraa_radxa_cm5_io()
mraa_radxa_cm5_io_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_cm5_io_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_cm5_io_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_cm5_io_pininfo(b, 3, 3, 27, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_D3");
mraa_radxa_cm5_io_pininfo(b, 3, 3, 27, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO3_D3");
mraa_radxa_cm5_io_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "5V");
mraa_radxa_cm5_io_pininfo(b, 5, 3, 26, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_D2");
mraa_radxa_cm5_io_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
Expand All @@ -136,7 +136,7 @@ mraa_radxa_cm5_io()
mraa_radxa_cm5_io_pininfo(b, 13, 4, 5, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO4_A5");
mraa_radxa_cm5_io_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND");
mraa_radxa_cm5_io_pininfo(b, 15, 4, 4, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_A4");
mraa_radxa_cm5_io_pininfo(b, 16, 1, 20, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO1_C4");
mraa_radxa_cm5_io_pininfo(b, 16, 1, 20, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO1_C4"); // Conflict with the fan's pwm11-m3
mraa_radxa_cm5_io_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "3V3");
mraa_radxa_cm5_io_pininfo(b, 18, 1, 29, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_D5");
mraa_radxa_cm5_io_pininfo(b, 19, 4, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A1");
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6 changes: 6 additions & 0 deletions src/arm/radxa_e25.c
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Expand Up @@ -98,16 +98,22 @@ mraa_radxa_e25()

b->pins[7].pwm.parent_id = 12; // pwm12-m0
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[11].pwm.parent_id = 14; // pwm14-m0
b->pins[11].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[13].pwm.parent_id = 1; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[13].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 7; // pwm7-m0
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;
b->pins[26].pwm.parent_id = 4; // pwm13-m0
b->pins[26].pwm.mux_total = 0;
b->pins[26].pwm.pinmap = 0;

mraa_radxa_e25_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_e25_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3.3V");
Expand Down
25 changes: 18 additions & 7 deletions src/arm/radxa_rock_3a.c
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Expand Up @@ -99,28 +99,39 @@ mraa_radxa_rock_3a()
return NULL;
}

b->pins[7].pwm.parent_id = 12; // PWM12_M0
b->pins[7].pwm.parent_id = 1; // PWM1_M1
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[11].pwm.parent_id = 14; // PWM14_M0
b->pins[11].pwm.mux_total = 0;
b->pins[11].pwm.pinmap = 0;
b->pins[13].pwm.parent_id = 15; // PWM15_IR_M0
b->pins[13].pwm.mux_total = 0;
b->pins[13].pwm.pinmap = 0;
b->pins[15].pwm.parent_id = 1; // PWM1_M0
b->pins[15].pwm.mux_total = 0;
b->pins[15].pwm.pinmap = 0;
b->pins[16].pwm.parent_id = 2; // PWM2_M1
b->pins[16].pwm.mux_total = 0;
b->pins[16].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 9; // PWM9_M0
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[19].pwm.parent_id = 15; // PWM15_IR_M1
b->pins[19].pwm.mux_total = 0;
b->pins[19].pwm.pinmap = 0;
b->pins[21].pwm.parent_id = 12; // PWM12_M1
b->pins[21].pwm.mux_total = 0;
b->pins[21].pwm.pinmap = 0;
b->pins[22].pwm.parent_id = 2; // PWM2_M0
b->pins[22].pwm.mux_total = 0;
b->pins[22].pwm.pinmap = 0;
b->pins[23].pwm.parent_id = 14; // PWM14_M1
b->pins[23].pwm.mux_total = 0;
b->pins[23].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 13; // PWM13_M1
b->pins[24].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // PWM9_M0
b->pins[18].pwm.mux_total = 0;
b->pins[16].pwm.parent_id = 2; // PWM2_M1
b->pins[16].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 1; // PWM1_M1
b->pins[7].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;

// hardware V1.3/V1.31
mraa_radxa_rock_3a_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
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35 changes: 23 additions & 12 deletions src/arm/radxa_rock_3b.c
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Expand Up @@ -97,28 +97,39 @@ mraa_radxa_rock_3b()
return NULL;
}

b->pins[15].pwm.parent_id = 1; // pwm1-m0
b->pins[15].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 1; // pwm1-m1
b->pins[7].pwm.mux_total = 0;
b->pins[22].pwm.parent_id = 2; // pwm2-m0
b->pins[22].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[11].pwm.parent_id = 14; // pwm14-m0
b->pins[11].pwm.mux_total = 0;
b->pins[11].pwm.pinmap = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[13].pwm.pinmap = 0;
b->pins[15].pwm.parent_id = 1; // pwm1-m0
b->pins[15].pwm.mux_total = 0;
b->pins[15].pwm.pinmap = 0;
b->pins[16].pwm.parent_id = 2; // pwm2-m1
b->pins[16].pwm.mux_total = 0;
b->pins[16].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 9; // pwm9-m0
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
b->pins[19].pwm.pinmap = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 14; // pwm14-m0
b->pins[11].pwm.mux_total = 0;
b->pins[21].pwm.pinmap = 0;
b->pins[22].pwm.parent_id = 2; // pwm2-m0
b->pins[22].pwm.mux_total = 0;
b->pins[22].pwm.pinmap = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
b->pins[23].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;

mraa_radxa_rock_3b_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_3b_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
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20 changes: 11 additions & 9 deletions src/arm/radxa_rock_3c.c
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Expand Up @@ -94,22 +94,24 @@ mraa_radxa_rock_3c()
return NULL;
}

b->pins[7].pwm.parent_id = 14; // pwm14-m0
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[16].pwm.parent_id = 8; // pwm8-m0
b->pins[16].pwm.mux_total = 0;
b->pins[16].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 9; // pwm9-m0
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 14; // pwm14-m0
b->pins[7].pwm.mux_total = 0;
b->pins[21].pwm.pinmap = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
b->pins[23].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;

mraa_radxa_rock_3c_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_3c_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
Expand All @@ -130,7 +132,7 @@ mraa_radxa_rock_3c()
mraa_radxa_rock_3c_pininfo(b, 16, 3, 9, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO03_B1");
mraa_radxa_rock_3c_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_3c_pininfo(b, 18, 3, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B2");
mraa_radxa_rock_3c_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C3");
mraa_radxa_rock_3c_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_C3"); // Pwm 15 channel 0 used by fan0
mraa_radxa_rock_3c_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 21, 4, 21, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C5");
mraa_radxa_rock_3c_pininfo(b, 22, 3, 17, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_C1");
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6 changes: 3 additions & 3 deletions src/arm/radxa_rock_5a.c
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Expand Up @@ -116,15 +116,15 @@ mraa_radxa_rock_5a()
b->pins[23].pwm.parent_id = 0; // PWM0_M2
b->pins[23].pwm.mux_total = 0;
b->pins[23].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 1; // PWM1_M2
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;
b->pins[27].pwm.parent_id = 6; // PWM6_M0
b->pins[27].pwm.mux_total = 0;
b->pins[27].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 7; // PWM7_M0
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 1; // PWM1_M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;

// AIO
b->aio_count = MRAA_RADXA_ROCK_5A_AIO_COUNT;
Expand Down
60 changes: 30 additions & 30 deletions src/arm/radxa_rock_5b.c
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Expand Up @@ -87,48 +87,48 @@ mraa_radxa_rock_5b()
return NULL;
}

b->pins[36].pwm.parent_id = 2; // PWM2_M1
b->pins[36].pwm.mux_total = 0;
b->pins[36].pwm.pinmap = 0;
b->pins[38].pwm.parent_id = 3; // PWM3_M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;
b->pins[3].pwm.parent_id = 15; // PWM15_M1
b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[5].pwm.parent_id = 14; // PWM14_M2
b->pins[5].pwm.mux_total = 0;
b->pins[5].pwm.pinmap = 0;
b->pins[7].pwm.parent_id = 15; // PWM15_M0
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[12].pwm.parent_id = 12; // PWM12_M0
b->pins[12].pwm.mux_total = 0;
b->pins[12].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 5; // PWM5_M2
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 6; // PWM6_M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[27].pwm.parent_id = 7; // PWM7_M3
b->pins[27].pwm.mux_total = 0;
b->pins[27].pwm.pinmap = 0;
b->pins[33].pwm.parent_id = 8; // PWM8_M0
b->pins[33].pwm.mux_total = 0;
b->pins[33].pwm.pinmap = 0;
b->pins[12].pwm.parent_id = 12; // PWM12_M0
b->pins[12].pwm.mux_total = 0;
b->pins[12].pwm.pinmap = 0;
b->pins[35].pwm.parent_id = 13; // PWM13_M0
b->pins[35].pwm.mux_total = 0;
b->pins[35].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 6; // PWM6_M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 15; // PWM15_M3
b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 13; // PWM13_M2
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 14; // PWM14_M0
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[5].pwm.parent_id = 14; // PWM14_M2
b->pins[5].pwm.mux_total = 0;
b->pins[5].pwm.pinmap = 0;
b->pins[7].pwm.parent_id = 15; // PWM15_M0
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[3].pwm.parent_id = 15; // PWM15_M1
b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 7; // PWM15_M3
b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0;
b->pins[33].pwm.parent_id = 8; // PWM8_M0
b->pins[33].pwm.mux_total = 0;
b->pins[33].pwm.pinmap = 0;
b->pins[35].pwm.parent_id = 13; // PWM13_M0
b->pins[35].pwm.mux_total = 0;
b->pins[35].pwm.pinmap = 0;
b->pins[36].pwm.parent_id = 2; // PWM2_M1
b->pins[36].pwm.mux_total = 0;
b->pins[36].pwm.pinmap = 0;
b->pins[38].pwm.parent_id = 3; // PWM3_M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;

b->aio_count = MRAA_RADXA_ROCK_5B_AIO_COUNT;
b->adc_raw = 10;
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