Labels

Application level functionality (examples, uses of XLS stack)

Pull requests that update bazel code

Blocking design work

Something isn't working or is incorrect

Related to build flow, build system, or build macros

An issue that could not be reproduced

Contributor agreement necessary, not present, see https://cla.developers.google.com

Tech debt reduction, factoring, consolidation, rework, etc.

Everything w.r.t. code quality, maintenance, TODOs

Related to emitting (System)Verilog.

Relating to Communicating Sequential Processes or Kahn Process Network style concurrency models

Predicting/modeling delays of target (backend) processes

Pull requests that update a dependency file

Improvements or additions to documentation

DSLX (domain specific language) implementation / front-end

DSLX auto-formatter

DSLX language server/protocol implementation

Syntax changes to DSLX

Bugs related to Type Inference v2

This issue or pull request already exists

Not yet confirmed as a duplicate but expected that it is.

New feature or request

Large: ~a week

Medium: ~1-3 days

Small: ~a day

eXtra Large: ~multi-week

eXtra Small: ~few hours

"Foreign Function" Interfacing (with SystemVerilog)