Add RV64D,RVB

README.en.md

@@ -45,8 +45,8 @@ Built for RISC-V developers, students and researchers.
 | RV32A     | ✅            |
 | RV64A     | ✅            |
 | RV128A    | ✅            |
-| RV64D     | ❌            |
-| RVB       | ❌            |
+| RV64D     | ✅            |
+| RVB       | ✅            |
 
 ## 🚀 Quick Start
 

README.md

@@ -43,8 +43,8 @@ RobustOne Online 是一款基于 WebAssembly 的在线 RISC-V 汇编反汇编工
 | RV32A     | ✅      |
 | RV64A     | ✅      |
 | RV128A    | ✅      |
-| RV64D     | ❌      |
-| RVB       | ❌      |
+| RV64D     | ✅      |
+| RVB       | ✅      |
 
 ## 🚀 快速开始
 

wasm-riscv-online/Cargo.toml

@@ -7,6 +7,10 @@ edition = "2018"
 [lib]
 crate-type = ["cdylib", "rlib"]
 
+[[bin]]
+name = "verify_features"
+path = "verify_features.rs"
+
 [features]
 default = ["console_error_panic_hook"]
 

wasm-riscv-online/src/asm/mod.rs

@@ -7,6 +7,8 @@ pub use rvzicsr::RVZicsr;
 pub use rva::RV32A;
 pub use rva::RV64A;
 pub use rva::RV128A;
+pub use rv64d::RV64D;
+pub use rvb::RVB;
 use crate::riscv::imm::{Imm, Uimm};
 
 pub mod rv32i;
@@ -15,6 +17,8 @@ pub mod rvc;
 pub mod rvf;
 pub mod rvzicsr;
 pub mod rva;
+pub mod rv64d;
+pub mod rvb;
 
 #[derive(Debug, Clone, Copy)]
 pub enum Instruction {
@@ -26,6 +30,8 @@ pub enum Instruction {
     RV32A(RV32A),
     RV64A(RV64A),
     RV128A(RV128A),
+    RV64D(RV64D),
+    RVB(RVB),
 }
 
 impl Instruction {
@@ -39,6 +45,8 @@ impl Instruction {
             Self::RV32A(rv32a) => rv32a.to_string(),
             Self::RV64A(rv64a) => rv64a.to_string(),
             Self::RV128A(rv128a) => rv128a.to_string(),
+            Self::RV64D(rv64d) => rv64d.to_string(),
+            Self::RVB(rvb) => rvb.to_string(),
         }
     }
 }
@@ -91,6 +99,28 @@ impl From<RV128A> for Instruction {
     }
 }
 
+impl From<RV64D> for Instruction {
+    fn from(src: RV64D) -> Instruction {
+        Instruction::RV64D(src)
+    }
+}
+
+impl From<RVB> for Instruction {
+    fn from(src: RVB) -> Instruction {
+        Instruction::RVB(src)
+    }
+}
+
+impl Instruction {
+    pub fn to_string(&self) -> String {
+        match self {
+            Self::RV64D(instr) => instr.to_string(),
+            Self::RVB(instr) => instr.to_string(),
+            _ => String::from("Unimplemented instruction"),
+        }
+    }
+}
+
 #[derive(Debug, Clone, Copy)]
 pub struct UType {
     pub rd: u8,
@@ -266,14 +296,24 @@ fn to_register(ins: u8) -> String {
 
 pub fn from_register(name: &str) -> Option<u8> {
     let s = name.trim().to_lowercase();
-    // xN numeric
+
+    // 浮点寄存器 - fN 格式
+    if let Some(num) = s.strip_prefix('f') {
+        if let Ok(n) = num.parse::<u8>() {
+            if n <= 31 { return Some(n); }
+        }
+    }
+
+    // 整数寄存器 - xN 格式
     if let Some(num) = s.strip_prefix('x') {
         if let Ok(n) = num.parse::<u8>() {
             if n <= 31 { return Some(n); }
         }
     }
+
     // ABI names
     match s.as_str() {
+        // 整数寄存器
         "zero" => Some(0),
         "ra" => Some(1),
         "sp" => Some(2),
@@ -306,6 +346,41 @@ pub fn from_register(name: &str) -> Option<u8> {
         "t4" => Some(29),
         "t5" => Some(30),
         "t6" => Some(31),
+
+        // 浮点寄存器
+        "ft0" => Some(0),
+        "ft1" => Some(1),
+        "ft2" => Some(2),
+        "ft3" => Some(3),
+        "ft4" => Some(4),
+        "ft5" => Some(5),
+        "ft6" => Some(6),
+        "ft7" => Some(7),
+        "fs0" => Some(8),
+        "fs1" => Some(9),
+        "fa0" => Some(10),
+        "fa1" => Some(11),
+        "fa2" => Some(12),
+        "fa3" => Some(13),
+        "fa4" => Some(14),
+        "fa5" => Some(15),
+        "fa6" => Some(16),
+        "fa7" => Some(17),
+        "fs2" => Some(18),
+        "fs3" => Some(19),
+        "fs4" => Some(20),
+        "fs5" => Some(21),
+        "fs6" => Some(22),
+        "fs7" => Some(23),
+        "fs8" => Some(24),
+        "fs9" => Some(25),
+        "fs10" => Some(26),
+        "fs11" => Some(27),
+        "ft8" => Some(28),
+        "ft9" => Some(29),
+        "ft10" => Some(30),
+        "ft11" => Some(31),
+
         _ => None,
     }
 }

wasm-riscv-online/src/asm/rv64d.rs

@@ -0,0 +1,72 @@
+#![allow(dead_code)]
+use std::fmt::Display;
+use crate::asm::{IType, RType, SType, R4Type, to_register};
+
+#[derive(Debug, Clone, Copy)]
+pub enum RV64D {
+    // Load/Store
+    Fld(IType),
+    Fsd(SType),
+
+    // FMADD Group
+    FmaddD(R4Type),
+    FmsubD(R4Type),
+    FnmsubD(R4Type),
+    FnmaddD(R4Type),
+
+    // Arithmetic
+    FaddD(RType),
+    FsubD(RType),
+    FmulD(RType),
+    FdivD(RType),
+    FsqrtD(RType),
+
+    // Comparisons
+    FeqD(RType),
+    FltD(RType),
+    FleD(RType),
+
+    // Min/Max
+    FminD(RType),
+    FmaxD(RType),
+
+    // Sign-Injection
+    FsgnjD(RType),
+    FsgnjnD(RType),
+    FsgnjxD(RType),
+
+    // Conversions (FP <-> Integer)
+    FcvtWD(RType),     // fcvt.w.d
+    FcvtWUD(RType),    // fcvt.wu.d
+    FcvtLD(RType),     // fcvt.l.d
+    FcvtLUD(RType),    // fcvt.lu.d
+    FcvtDW(RType),     // fcvt.d.w
+    FcvtDWU(RType),    // fcvt.d.wu
+    FcvtDL(RType),     // fcvt.d.l
+    FcvtDLU(RType),    // fcvt.d.lu
+
+    // Conversions (Single <-> Double)
+    FcvtSD(RType),     // fcvt.s.d
+    FcvtDS(RType),     // fcvt.d.s
+
+    // Move and Classify
+    FmvXD(RType),      // fmv.x.d
+    FmvDX(RType),      // fmv.d.x
+    FclassD(RType),    // fclass.d
+}
+
+impl RV64D {
+    pub fn to_string(&self) -> String {
+        match self {
+            Self::Fld(i) => format!("fld f{}, {:?}({})", i.rd, i.imm, to_register(i.rs1)),
+            Self::Fsd(s) => format!("fsd f{}, {:?}({})", s.rs2, s.imm, to_register(s.rs1)),
+            _ => String::from("RV64D instruction"),
+        }
+    }
+}
+
+impl Display for RV64D {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        write!(f, "{}", self.to_string())
+    }
+}

wasm-riscv-online/src/asm/rvb.rs

@@ -0,0 +1,91 @@
+#![allow(dead_code)]
+use std::fmt::Display;
+use crate::asm::{IType, RType, BType, to_register};
+
+#[derive(Debug, Clone, Copy)]
+pub enum RVB {
+    // Basic Bit Manipulation
+    // Shifts with Variable Shift Amount
+    Sllw(RType),     // Shift Left Logical Word
+    Srlw(RType),     // Shift Right Logical Word
+    Sraw(RType),     // Shift Right Arithmetic Word
+    Ror(RType),      // Rotate Right
+    Rori(IType),     // Rotate Right Immediate
+    Rorw(RType),     // Rotate Right Word
+    Roriw(IType),    // Rotate Right Immediate Word
+
+    // Bitwise Operations
+    Andn(RType),     // AND NOT
+    Orn(RType),      // OR NOT
+    Xnor(RType),     // XNOR
+
+    // Single-Bit Instructions
+    Bset(RType),     // Bit Set
+    Bseti(IType),    // Bit Set Immediate
+    Bclr(RType),     // Bit Clear
+    Bclri(IType),    // Bit Clear Immediate
+    Binv(RType),     // Bit Invert
+    Binvi(IType),    // Bit Invert Immediate
+    Bext(RType),     // Bit Extract
+    Bexti(IType),    // Bit Extract Immediate
+
+    // Bit Field Instructions
+    BEXT(RType),     // Bit Field Extract
+    BEXTI(IType),    // Bit Field Extract Immediate
+    BCLR(RType),     // Bit Field Clear
+    BCLRI(IType),    // Bit Field Clear Immediate
+    BSET(RType),     // Bit Field Set
+    BSETI(IType),    // Bit Field Set Immediate
+    BINVERT(RType),  // Bit Field Invert
+    BINVERTI(IType), // Bit Field Invert Immediate
+
+    // Bit Count Instructions
+    Cpop(RType),     // Count Population
+    Cpopw(RType),    // Count Population Word
+    Ctz(RType),      // Count Trailing Zeros
+    CtzW(RType),     // Count Trailing Zeros Word
+    Clz(RType),      // Count Leading Zeros
+    ClzW(RType),     // Count Leading Zeros Word
+    FFS(RType),      // Find First Set
+    FFSW(RType),     // Find First Set Word
+
+    // Single-Bit Instructions (Word variants)
+    BsetW(RType),    // Bit Set Word
+    BsetiW(IType),   // Bit Set Immediate Word
+    BclrW(RType),    // Bit Clear Word
+    BclriW(IType),   // Bit Clear Immediate Word
+    BinvW(RType),    // Bit Invert Word
+    BinviW(IType),   // Bit Invert Immediate Word
+    BextW(RType),    // Bit Extract Word
+    BextiW(IType),   // Bit Extract Immediate Word
+
+    // Deposit Instructions
+    Pack(RType),     // Pack
+    PackW(RType),    // Pack Word
+
+    // Bit Manipulation - Advanced
+    Grevi(RType),    // Generalized Reverse Immediate
+    GreviW(RType),   // Generalized Reverse Immediate Word
+    Gorb(RType),     // Generalized OR
+    Gorhi(RType),    // Generalized OR High Immediate
+    GorbW(RType),    // Generalized OR Word
+    GorhiW(RType),   // Generalized OR High Immediate Word
+    Gxori(RType),    // Generalized XOR Immediate
+    GxoriW(RType),   // Generalized XOR Immediate Word
+}
+
+impl RVB {
+    pub fn to_string(&self) -> String {
+        match self {
+            Self::Bset(r) => format!("bset {}, {}, {}", to_register(r.rd), to_register(r.rs1), r.rs2),
+            Self::Bext(r) => format!("bext {}, {}, {}", to_register(r.rd), to_register(r.rs1), r.rs2),
+            _ => String::from("RVB instruction"),
+        }
+    }
+}
+
+impl Display for RVB {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        write!(f, "{}", self.to_string())
+    }
+}