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[LLVM][AArch64] Add "u" variants of sve.[s,u]hadd intrinsics
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13 files changed

+433
-84
lines changed

13 files changed

+433
-84
lines changed

‎clang/include/clang/Basic/arm_sve.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1280,10 +1280,10 @@ defm SVQSUB_S : SInstZPZZ<"svqsub", "csli", "aarch64_sve_sqsub", "aarch64
12801280
defm SVQSUB_U : SInstZPZZ<"svqsub", "UcUsUiUl", "aarch64_sve_uqsub", "aarch64_sve_uqsub_u">;
12811281
defm SVQSUBR_S : SInstZPZZ<"svqsubr", "csli", "aarch64_sve_sqsubr", "aarch64_sve_sqsub_u", [ReverseMergeAnyBinOp]>;
12821282
defm SVQSUBR_U : SInstZPZZ<"svqsubr", "UcUsUiUl", "aarch64_sve_uqsubr", "aarch64_sve_uqsub_u", [ReverseMergeAnyBinOp]>;
1283-
defm SVHSUB_S : SInstZPZZ<"svhsub", "csli", "aarch64_sve_shsub", "aarch64_sve_shsub">;
1284-
defm SVHSUB_U : SInstZPZZ<"svhsub", "UcUsUiUl", "aarch64_sve_uhsub", "aarch64_sve_uhsub">;
1285-
defm SVHSUBR_S : SInstZPZZ<"svhsubr", "csli", "aarch64_sve_shsubr", "aarch64_sve_shsubr">;
1286-
defm SVHSUBR_U : SInstZPZZ<"svhsubr", "UcUsUiUl", "aarch64_sve_uhsubr", "aarch64_sve_uhsubr">;
1283+
defm SVHSUB_S : SInstZPZZ<"svhsub", "csli", "aarch64_sve_shsub", "aarch64_sve_shsub_u">;
1284+
defm SVHSUB_U : SInstZPZZ<"svhsub", "UcUsUiUl", "aarch64_sve_uhsub", "aarch64_sve_uhsub_u">;
1285+
defm SVHSUBR_S : SInstZPZZ<"svhsubr", "csli", "aarch64_sve_shsubr", "aarch64_sve_shsub_u", [ReverseMergeAnyBinOp]>;
1286+
defm SVHSUBR_U : SInstZPZZ<"svhsubr", "UcUsUiUl", "aarch64_sve_uhsubr", "aarch64_sve_uhsub_u", [ReverseMergeAnyBinOp]>;
12871287

12881288
defm SVQABS : SInstZPZ<"svqabs", "csil", "aarch64_sve_sqabs">;
12891289
defm SVQNEG : SInstZPZ<"svqneg", "csil", "aarch64_sve_sqneg">;

‎clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_hsub.c‎

Lines changed: 32 additions & 32 deletions
Large diffs are not rendered by default.

‎clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_hsubr.c‎

Lines changed: 32 additions & 32 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2435,6 +2435,7 @@ def int_aarch64_sve_stnt1_scatter_scalar_offset : AdvSIMD_ScatterStore_VS_Intri
24352435
def int_aarch64_sve_saba : AdvSIMD_3VectorArg_Intrinsic<[IntrSpeculatable]>;
24362436
def int_aarch64_sve_shadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24372437
def int_aarch64_sve_shsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
2438+
def int_aarch64_sve_shsub_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24382439
def int_aarch64_sve_shsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24392440
def int_aarch64_sve_sli : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>;
24402441
def int_aarch64_sve_sqabs : AdvSIMD_Merged1VectorArg_Intrinsic<[IntrSpeculatable]>;
@@ -2467,6 +2468,7 @@ def int_aarch64_sve_suqadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpecul
24672468
def int_aarch64_sve_uaba : AdvSIMD_3VectorArg_Intrinsic<[IntrSpeculatable]>;
24682469
def int_aarch64_sve_uhadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24692470
def int_aarch64_sve_uhsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
2471+
def int_aarch64_sve_uhsub_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24702472
def int_aarch64_sve_uhsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24712473
def int_aarch64_sve_uqadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;
24722474
def int_aarch64_sve_uqrshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>;

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3838,12 +3838,15 @@ let Predicates = [HasSVE2_or_SME] in {
38383838
// SVE2 integer halving add/subtract (predicated)
38393839
defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd", AArch64shadd>;
38403840
defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd", AArch64uhadd>;
3841-
defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub", int_aarch64_sve_shsub>;
3842-
defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub", int_aarch64_sve_uhsub>;
3841+
defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub", int_aarch64_sve_shsub, "SHSUB_ZPZZ", DestructiveBinaryCommWithRev, "SHSUBR_ZPmZ">;
3842+
defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub", int_aarch64_sve_uhsub, "UHSUB_ZPZZ", DestructiveBinaryCommWithRev, "UHSUBR_ZPmZ">;
38433843
defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd", AArch64srhadd>;
38443844
defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd", AArch64urhadd>;
3845-
defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr", int_aarch64_sve_shsubr>;
3846-
defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr", int_aarch64_sve_uhsubr>;
3845+
defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr", int_aarch64_sve_shsubr, "SHSUBR_ZPZZ", DestructiveBinaryCommWithRev, "SHSUB_ZPmZ", /*isReverseInstr*/ 1>;
3846+
defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr", int_aarch64_sve_uhsubr, "UHSUBR_ZPZZ", DestructiveBinaryCommWithRev, "UHSUB_ZPmZ", /*isReverseInstr*/ 1>;
3847+
3848+
defm SHSUB_ZPZZ : sve_int_bin_pred_bhsd<int_aarch64_sve_shsub_u>;
3849+
defm UHSUB_ZPZZ : sve_int_bin_pred_bhsd<int_aarch64_sve_uhsub_u>;
38473850

38483851
// SVE2 integer pairwise add and accumulate long
38493852
defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp", int_aarch64_sve_sadalp>;

‎llvm/lib/Target/AArch64/AArch64SchedA510.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -652,7 +652,7 @@ def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>],
652652
"^(ADD|SUB|SUBR)_ZI_[BHSD]",
653653
"^ADR_[SU]XTW_ZZZ_D_[0123]",
654654
"^ADR_LSL_ZZZ_[SD]_[0123]",
655-
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]")>;
655+
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]")>;
656656
def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>],
657657
(instregex "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
658658
"^SADDLBT_ZZZ_[HSD]",

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1662,7 +1662,7 @@ def : InstRW<[N2Write_2c_1V],
16621662
"^ADR_LSL_ZZZ_[SD]_[0123]",
16631663
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
16641664
"^SADDLBT_ZZZ_[HSD]",
1665-
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
1665+
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
16661666
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;
16671667

16681668
// Arithmetic, complex

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1752,7 +1752,7 @@ def : InstRW<[N3Write_2c_1V],
17521752
"^ADR_LSL_ZZZ_[SD]_[0123]",
17531753
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
17541754
"^SADDLBT_ZZZ_[HSD]",
1755-
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
1755+
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
17561756
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;
17571757

17581758
// Arithmetic, complex

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2125,7 +2125,7 @@ def : InstRW<[V2Write_2c_1V],
21252125
"^ADR_LSL_ZZZ_[SD]_[0123]",
21262126
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]",
21272127
"^SADDLBT_ZZZ_[HSD]",
2128-
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]",
2128+
"^[SU]H(ADD|SUB|SUBR)_(ZPmZ|ZPZZ)_[BHSD]",
21292129
"^SSUBL(BT|TB)_ZZZ_[HSD]")>;
21302130

21312131
// Arithmetic, complex

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1446,6 +1446,10 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
14461446
case Intrinsic::aarch64_sve_orr:
14471447
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_orr_u)
14481448
.setMatchingIROpcode(Instruction::Or);
1449+
case Intrinsic::aarch64_sve_shsub:
1450+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_shsub_u);
1451+
case Intrinsic::aarch64_sve_shsubr:
1452+
return SVEIntrinsicInfo::defaultMergingOp();
14491453
case Intrinsic::aarch64_sve_sqrshl:
14501454
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqrshl_u);
14511455
case Intrinsic::aarch64_sve_sqshl:
@@ -1454,6 +1458,10 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
14541458
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqsub_u);
14551459
case Intrinsic::aarch64_sve_srshl:
14561460
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_srshl_u);
1461+
case Intrinsic::aarch64_sve_uhsub:
1462+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uhsub_u);
1463+
case Intrinsic::aarch64_sve_uhsubr:
1464+
return SVEIntrinsicInfo::defaultMergingOp();
14571465
case Intrinsic::aarch64_sve_uqrshl:
14581466
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uqrshl_u);
14591467
case Intrinsic::aarch64_sve_uqshl:

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