Avoid _ret symbol and apply suggested documentation improvements

Author: Tarcisio Fischer

lld/ELF/AArch64ErrataFix.cpp

@@ -370,7 +370,7 @@ static uint64_t scanCortexA53Errata843419(InputSection *isec, uint64_t &off,
 
 class elf::Patch843419Section final : public SyntheticSection {
 public:
-  Patch843419Section(Ctx &, InputSection *p, uint64_t off);
+  Patch843419Section(Ctx &, InputSection *p, uint64_t off, Symbol* patcheeCodeSym);
 
   void writeTo(uint8_t *buf) override;
 
@@ -388,11 +388,9 @@ class elf::Patch843419Section final : public SyntheticSection {
   uint64_t patcheeOffset;
   // A label for the start of the Patch that we can use as a relocation target.
   Symbol *patchSym;
-  // A label for the return location.
-  Symbol *retSym;
 };
 
-Patch843419Section::Patch843419Section(Ctx &ctx, InputSection *p, uint64_t off)
+Patch843419Section::Patch843419Section(Ctx &ctx, InputSection *p, uint64_t off, Symbol* patcheeCodeSym)
     : SyntheticSection(ctx, ".text.patch", SHT_PROGBITS,
                        SHF_ALLOC | SHF_EXECINSTR, 4),
       patchee(p), patcheeOffset(off) {
@@ -401,12 +399,8 @@ Patch843419Section::Patch843419Section(Ctx &ctx, InputSection *p, uint64_t off)
       ctx, ctx.saver.save("__CortexA53843419_" + utohexstr(getLDSTAddr())),
       STT_FUNC, 0, getSize(), *this);
   addSyntheticLocal(ctx, ctx.saver.save("$x"), STT_NOTYPE, 0, 0, *this);
-  retSym = addSyntheticLocal(
-      ctx, ctx.saver.save("__CortexA53843419_" + utohexstr(getLDSTAddr()) + "_ret"),
-      STT_FUNC, off + 4, 4, *p);
-
-  // Relocation must be created as soon as possible, so it'll be picked up.
-  addReloc({R_PC, R_AARCH64_JUMP26, 4, 0, retSym});
+  int64_t retToPatcheeSymOffset = (getLDSTAddr() - p->getVA(dyn_cast<Defined>(patcheeCodeSym)->value)) + 4;
+  addReloc({R_PC, R_AARCH64_JUMP26, 4, retToPatcheeSymOffset, patcheeCodeSym});
 }
 
 uint64_t Patch843419Section::getLDSTAddr() const {
@@ -418,10 +412,6 @@ void Patch843419Section::writeTo(uint8_t *buf) {
   // patchee Section.
   write32le(buf, read32le(patchee->content().begin() + patcheeOffset));
 
-  // Note: The jump back was configured in this classe's constructor, and
-  // will be filled by the relocation. Adding the relocation here would be
-  // too late.
-
   // Apply relocations
   ctx.target->relocateAlloc(*this, buf);
 }
@@ -462,7 +452,7 @@ void AArch64Err843419Patcher::init() {
   // the same type. For example we must remove the redundant $d.1 from $x.0
   // $d.0 $d.1 $x.1.
   for (auto &kv : sectionMap) {
-    std::vector<const Defined *> &mapSyms = kv.second;
+    std::vector<Defined *> &mapSyms = kv.second;
     llvm::stable_sort(mapSyms, [](const Defined *a, const Defined *b) {
       return a->value < b->value;
     });
@@ -536,7 +526,8 @@ void AArch64Err843419Patcher::insertPatches(
 // Patches that we need to insert.
 static void implementPatch(Ctx &ctx, uint64_t adrpAddr, uint64_t patcheeOffset,
                            InputSection *isec,
-                           std::vector<Patch843419Section *> &patches) {
+                           std::vector<Patch843419Section *> &patches,
+                           Symbol* patcheeCodeSym) {
   // There may be a relocation at the same offset that we are patching. There
   // are four cases that we need to consider.
   // Case 1: R_AARCH64_JUMP26 branch relocation. We have already patched this
@@ -561,7 +552,7 @@ static void implementPatch(Ctx &ctx, uint64_t adrpAddr, uint64_t patcheeOffset,
   Log(ctx) << "detected cortex-a53-843419 erratum sequence starting at " <<
       utohexstr(adrpAddr) << " in unpatched output.";
 
-  auto *ps = make<Patch843419Section>(ctx, isec, patcheeOffset);
+  auto *ps = make<Patch843419Section>(ctx, isec, patcheeOffset, patcheeCodeSym);
   patches.push_back(ps);
 
   auto makeRelToPatch = [](uint64_t offset, Symbol *patchSym) {
@@ -591,7 +582,7 @@ AArch64Err843419Patcher::patchInputSectionDescription(
     // mapping symbols of the same type. Our range of executable instructions to
     // scan is therefore [codeSym->value, dataSym->value) or [codeSym->value,
     // section size).
-    std::vector<const Defined *> &mapSyms = sectionMap[isec];
+    std::vector<Defined *> &mapSyms = sectionMap[isec];
 
     auto codeSym = mapSyms.begin();
     while (codeSym != mapSyms.end()) {
@@ -604,7 +595,7 @@ AArch64Err843419Patcher::patchInputSectionDescription(
         uint64_t startAddr = isec->getVA(off);
         if (uint64_t patcheeOffset =
                 scanCortexA53Errata843419(isec, off, limit))
-          implementPatch(ctx, startAddr, patcheeOffset, isec, patches);
+          implementPatch(ctx, startAddr, patcheeOffset, isec, patches, dyn_cast<Symbol>(*codeSym));
       }
       if (dataSym == mapSyms.end())
         break;

lld/ELF/AArch64ErrataFix.h

@@ -39,7 +39,7 @@ class AArch64Err843419Patcher {
   // A cache of the mapping symbols defined by the InputSection sorted in order
   // of ascending value with redundant symbols removed. These describe
   // the ranges of code and data in an executable InputSection.
-  llvm::DenseMap<InputSection *, std::vector<const Defined *>> sectionMap;
+  llvm::DenseMap<InputSection *, std::vector<Defined *>> sectionMap;
 
   bool initialized = false;
 };

lld/ELF/Arch/AArch64.cpp

@@ -49,9 +49,8 @@ bool elf::isAArch64BTILandingPad(Ctx &ctx, Symbol &s, int64_t a) {
     return true;
   const uint8_t *buf = isec->content().begin();
   // Synthetic sections may have a size but empty data - Assume that they won't contain a landing pad
-  if (buf == nullptr && dyn_cast<SyntheticSection>(isec) != nullptr) {
+  if (buf == nullptr && isa<SyntheticSection>(isec))
     return false;
-  }
 
   const uint32_t instr = read32le(buf + off);
   // All BTI instructions are HINT instructions which all have same encoding

lld/ELF/Relocations.cpp

@@ -2010,6 +2010,12 @@ ThunkSection *ThunkCreator::addThunkSection(OutputSection *os,
     // 2.) The InputSectionDescription is larger than 4 KiB. This will prevent
     //     any assertion failures that an InputSectionDescription is < 4 KiB
     //     in size.
+    //
+    // isPrefix is a ThunkSection explicitly inserted before its target
+    // section. We suppress the rounding up of the size of these ThunkSections
+    // as unlike normal ThunkSections, they are small in size, but when BTI is
+    // enabled very frequent. This can bloat code-size and push the errata
+    // patches out of branch range.
     uint64_t isdSize = isd->sections.back()->outSecOff +
                        isd->sections.back()->getSize() -
                        isd->sections.front()->outSecOff;

lld/test/ELF/aarch64-cortex-a53-843419-address.s

@@ -41,7 +41,6 @@
 // CHECK-NEXT:      ff8:        d0000020        adrp    x0, 0x6000
 // CHECK-NEXT:      ffc:        f9400021        ldr             x1, [x1]
 // CHECK-NEXT:     1000:        14000ff9        b       0x4fe4
-// CHECK: <__CortexA53843419_1000_ret>:
 // CHECK-NEXT:     1004:        d65f03c0        ret
         .section .text.01, "ax", %progbits
         .balign 4096
@@ -64,7 +63,6 @@ $x.999:
 // CHECK-NEXT:     1ffc:        b0000020        adrp    x0, 0x6000
 // CHECK-NEXT:     2000:        bd400021        ldr             s1, [x1]
 // CHECK-NEXT:     2004:        14000bfa        b       0x4fec
-// CHECK: <__CortexA53843419_2004_ret>:
 // CHECK-NEXT:     2008:        d65f03c0        ret
         .globl t3_ffc_ldrsimd
         .type t3_ffc_ldrsimd, %function
@@ -102,7 +100,6 @@ t3_ff8_ldralldata:
 // CHECK-NEXT:     3ff8:        f0000000        adrp    x0, 0x6000
 // CHECK-NEXT:     3ffc:        f9400021        ldr             x1, [x1]
 // CHECK-NEXT:     4000:        140003fd        b       0x4ff4
-// CHECK: <__CortexA53843419_4000_ret>:
 // CHECK-NEXT:     4004:        d65f03c0        ret
         .space 4096 - 12
         .globl t3_ffc_ldr
@@ -135,7 +132,6 @@ t3_ff8_ldralldata:
 // CHECK-NEXT:     4ffc:        d0000000        adrp    x0, 0x6000
 // CHECK-NEXT:     5000:        f9000021        str             x1, [x1]
 // CHECK-NEXT:     5004:        140003fb        b       0x5ff0
-// CHECK: <__CortexA53843419_5004_ret>:
 // CHECK-NEXT:     5008:        d65f03c0        ret
 
         .section .newisd, "ax", %progbits
@@ -161,7 +157,6 @@ t3_ffc_str:
 // CHECK-NEXT:     5ff8:        b0000000        adrp    x0, 0x6000
 // CHECK-NEXT:     5ffc:        f9000021        str             x1, [x1]
 // CHECK-NEXT:     6000:        14000003        b       0x600c
-// CHECK: <__CortexA53843419_6000_ret>:
 // CHECK-NEXT:     6004:        d65f03c0        ret
 
         .section .newos, "ax", %progbits

lld/test/ELF/aarch64-cortex-a53-843419-large.s

@@ -45,7 +45,6 @@ t3_ff8_ldr:
 // CHECK3-NEXT:    211ff8:       f00400e0        adrp    x0, 0x8230000
 // CHECK3-NEXT:    211ffc:       f9400021        ldr     x1, [x1]
 // CHECK3-NEXT:    212000:       15800802        b       0x6214008
-// CHECK3: <__CortexA53843419_211000_ret>:
 // CHECK3-NEXT:    212004:       d65f03c0        ret
 
         .section .text.04, "ax", %progbits
@@ -67,7 +66,6 @@ t3_ff8_str:
 // CHECK4-NEXT:  4213ff8:       b00200e0        adrp    x0, 0x8230000
 // CHECK4-NEXT:  4213ffc:       f9400021        ldr     x1, [x1]
 // CHECK4-NEXT:  4214000:       14800004        b       0x6214010
-// CHECK4: <__CortexA53843419_4213000_ret>:
 // CHECK4-NEXT:  4214004:       d65f03c0        ret
 
         .section .text.06, "ax", %progbits
@@ -107,7 +105,6 @@ t3_ffc_ldr:
 // CHECK7-NEXT:  8211ffc:       f00000e0        adrp    x0, 0x8230000
 // CHECK7-NEXT:  8212000:       f9400021        ldr     x1, [x1]
 // CHECK7-NEXT:  8212004:       14000002        b       0x821200c
-// CHECK7: <__CortexA53843419_8212004_ret>:
 // CHECK7-NEXT:  8212008:       d65f03c0        ret
 // CHECK7: <__CortexA53843419_8212004>:
 // CHECK7-NEXT:  821200c:       f9400000        ldr     x0, [x0]