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[LLVM][AArch64] Remove hasNoSchedulingInfo from SVE pseudo instructions. (#171487)
These should always have the same schediling information as their real instruction counterparts. Removing this property means we'll catch missing entries when building the compiler. Also extends AArch64SVESchedPseudoTest coverage to include all existing CPU that support SVE.
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10 files changed

+51
-41
lines changed

10 files changed

+51
-41
lines changed

llvm/lib/Target/AArch64/AArch64SchedA320.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -639,7 +639,7 @@ def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PTRUES_[BHSD
639639
def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
640640

641641
// Predicate test
642-
def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs PTEST_PP)>;
642+
def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
643643

644644
// Predicate transpose
645645
def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^TRN[12]_PPP_[BHSDQ]")>;

llvm/lib/Target/AArch64/AArch64SchedA510.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -617,7 +617,7 @@ def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^PTRUES_[BHS
617617
def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
618618

619619
// Predicate test
620-
def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instrs PTEST_PP)>;
620+
def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
621621

622622
// Predicate transpose
623623
def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^TRN[12]_PPP_[BHSDQ]")>;

llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1625,7 +1625,7 @@ def : InstRW<[N2Write_3c_1M], (instregex "^PTRUES_[BHSD]$")>;
16251625
def : InstRW<[N2Write_3c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;
16261626

16271627
// Predicate test
1628-
def : InstRW<[N2Write_1c_1M], (instrs PTEST_PP)>;
1628+
def : InstRW<[N2Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
16291629

16301630
// Predicate transpose
16311631
def : InstRW<[N2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;

llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1715,7 +1715,7 @@ def : InstRW<[N3Write_0or2c_1M], (instregex "^PTRUES_[BHSD]")>;
17151715
def : InstRW<[N3Write_2c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;
17161716

17171717
// Predicate test
1718-
def : InstRW<[N3Write_1c_1M], (instrs PTEST_PP)>;
1718+
def : InstRW<[N3Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
17191719

17201720
// Predicate transpose
17211721
def : InstRW<[N3Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;

llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1481,7 +1481,7 @@ def : InstRW<[V1Write_2c_1M0], (instregex "^REV_PP_[BHSD]$",
14811481

14821482
// Predicate set/initialize/find next
14831483
// Predicate unpack and widen
1484-
def : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP,
1484+
def : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST,
14851485
PUNPKHI_PP, PUNPKLO_PP)>;
14861486

14871487
// Predicate select

llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2088,7 +2088,7 @@ def : InstRW<[V2Write_3c_2M], (instregex "^PTRUES_[BHSD]")>;
20882088
def : InstRW<[V2Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
20892089

20902090
// Predicate test
2091-
def : InstRW<[V2Write_1c_1M], (instrs PTEST_PP)>;
2091+
def : InstRW<[V2Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
20922092

20932093
// Predicate transpose
20942094
def : InstRW<[V2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;

llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2017,7 +2017,7 @@ def : InstRW<[V3Write_2c_1M], (instregex "^PTRUES_[BHSD]")>;
20172017
def : InstRW<[V3Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
20182018

20192019
// Predicate test
2020-
def : InstRW<[V3Write_1c_1M], (instrs PTEST_PP)>;
2020+
def : InstRW<[V3Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
20212021

20222022
// Predicate transpose
20232023
def : InstRW<[V3Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;

llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1945,7 +1945,7 @@ def : InstRW<[V3AEWrite_2c_1M], (instregex "^PTRUES_[BHSD]")>;
19451945
def : InstRW<[V3AEWrite_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
19461946

19471947
// Predicate test
1948-
def : InstRW<[V3AEWrite_1c_1M], (instrs PTEST_PP)>;
1948+
def : InstRW<[V3AEWrite_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
19491949

19501950
// Predicate transpose
19511951
def : InstRW<[V3AEWrite_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 30 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -800,45 +800,43 @@ class SVEInstr2Rev<string name1, string name2, bit name1IsReverseInstr> {
800800
//
801801
// Pseudos for destructive operands
802802
//
803-
let hasNoSchedulingInfo = 1 in {
804-
class PredTwoOpPseudo<string name, ZPRRegOp zprty,
805-
FalseLanesEnum flags = FalseLanesNone>
806-
: SVEPseudo2Instr<name, 0>,
807-
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
808-
let FalseLanes = flags;
809-
}
810803

811-
class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
812-
FalseLanesEnum flags = FalseLanesNone>
813-
: SVEPseudo2Instr<name, 0>,
814-
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
815-
let FalseLanes = flags;
816-
}
804+
class PredTwoOpPseudo<string name, ZPRRegOp zprty,
805+
FalseLanesEnum flags = FalseLanesNone>
806+
: SVEPseudo2Instr<name, 0>,
807+
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
808+
let FalseLanes = flags;
809+
}
817810

818-
class PredThreeOpPseudo<string name, ZPRRegOp zprty,
819-
FalseLanesEnum flags = FalseLanesNone>
820-
: SVEPseudo2Instr<name, 0>,
821-
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
822-
let FalseLanes = flags;
823-
}
811+
class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
812+
FalseLanesEnum flags = FalseLanesNone>
813+
: SVEPseudo2Instr<name, 0>,
814+
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
815+
let FalseLanes = flags;
816+
}
824817

825-
class UnpredRegImmPseudo<ZPRRegOp zprty, Operand immty>
826-
: SVEPseudo2Instr<NAME, 0>,
827-
Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
828-
}
818+
class PredThreeOpPseudo<string name, ZPRRegOp zprty,
819+
FalseLanesEnum flags = FalseLanesNone>
820+
: SVEPseudo2Instr<name, 0>,
821+
Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
822+
let FalseLanes = flags;
823+
}
824+
825+
class UnpredRegImmPseudo<ZPRRegOp zprty, Operand immty>
826+
: SVEPseudo2Instr<NAME, 0>,
827+
Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
829828
}
830829

831830
//
832831
// Pseudos for passthru operands
833832
//
834-
let hasNoSchedulingInfo = 1 in {
835-
class PredOneOpPassthruPseudo<string name, ZPRRegOp zprty,
836-
FalseLanesEnum flags = FalseLanesNone>
837-
: SVEPseudo2Instr<name, 0>,
838-
Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPR3bAny:$Pg, zprty:$Zs), []> {
839-
let FalseLanes = flags;
840-
let Constraints = !if(!eq(flags, FalseLanesZero), "$Zd = $Passthru,@earlyclobber $Zd", "");
841-
}
833+
834+
class PredOneOpPassthruPseudo<string name, ZPRRegOp zprty,
835+
FalseLanesEnum flags = FalseLanesNone>
836+
: SVEPseudo2Instr<name, 0>,
837+
Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPR3bAny:$Pg, zprty:$Zs), []> {
838+
let FalseLanes = flags;
839+
let Constraints = !if(!eq(flags, FalseLanesZero), "$Zd = $Passthru,@earlyclobber $Zd", "");
842840
}
843841

844842
//===----------------------------------------------------------------------===//
@@ -901,7 +899,7 @@ multiclass sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op,
901899
SDPatternOperator op_any, SDPatternOperator op_first> {
902900
def NAME : sve_int_ptest<opc, asm, op>;
903901

904-
let hasNoSchedulingInfo = 1, isCompare = 1, Defs = [NZCV] in {
902+
let isCompare = 1, Defs = [NZCV] in {
905903
def _ANY : Pseudo<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
906904
[(set NZCV, (op_any (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn)))]>,
907905
PseudoInstExpansion<(!cast<Instruction>(NAME) PPRAny:$Pg, PPR8:$Pn)>;

llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,11 +103,15 @@ void runSVEPseudoTestForCPU(const std::string &CPU) {
103103
}
104104

105105
// TODO : Add more CPUs that support SVE/SVE2
106+
TEST(AArch64SVESchedPseudoTesta320, IsCorrect) {
107+
runSVEPseudoTestForCPU("cortex-a320");
108+
}
109+
106110
TEST(AArch64SVESchedPseudoTesta510, IsCorrect) {
107111
runSVEPseudoTestForCPU("cortex-a510");
108112
}
109113

110-
TEST(AArch64SVESchedPseudoTestn1, IsCorrect) {
114+
TEST(AArch64SVESchedPseudoTestn2, IsCorrect) {
111115
runSVEPseudoTestForCPU("neoverse-n2");
112116
}
113117

@@ -123,4 +127,12 @@ TEST(AArch64SVESchedPseudoTestv2, IsCorrect) {
123127
runSVEPseudoTestForCPU("neoverse-v2");
124128
}
125129

130+
TEST(AArch64SVESchedPseudoTestv3, IsCorrect) {
131+
runSVEPseudoTestForCPU("neoverse-v3");
132+
}
133+
134+
TEST(AArch64SVESchedPseudoTestv3ae, IsCorrect) {
135+
runSVEPseudoTestForCPU("neoverse-v3ae");
136+
}
137+
126138
} // namespace

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