Update VTR to latest & Add strong testcases to validate direct connections across subtiles

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

See details in verilog-to-routing/vtr-verilog-to-routing#3318

What does this pull request change?

This PR improves in the following aspects:

Three new testcases have been added to the strong regression tests, each of which validate the new feature

• DSP and BRAM sub-tiles are stacked in the same tile. The starting point of direct connections come from the DSP (the 3rd sub-tile) and ends at the BRAMs (the 1st and 2nd sub-tiles)
• CLB, DSP and BRAM sub-tiles are stacked in the same tile. The starting of direction connections come from the DSP (the 2nd sub-tile) and ends at the BRAMs (the 3rd and 4th sub-tiles)
• CLB, DSP and BRAM sub-tiles are stacked in the same tile. The starting of direction connections come from the DSP (the 4th sub-tile) and ends at the BRAMs (the 2nd and 3rd sub-tiles)

Added 3 new architecture files and a blif benchmark to validate the DSP-to-RAM direct connectionso

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.