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This brings out a port called 'debug_mode_o' from the core and at the top, signifying the state of debug mode when IBEX is connected to other peripherals dependent on the debug mode to update their operation like halt, etc. No functional changes to it.
marnovandermaas
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marnovandermaas
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Would you mind explaining what use-case you have for this? I'm unsure why a peripheral would need to know about whether the Ibex is in debug mode or not.
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@marnovandermaas We have timers which need to enter the halt mode based on the processor's debug state. This port is tapped out of IBEX to feed into the timers to enable them to enter into the halt mode and exit based on the processor's state. |
marnovandermaas
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marnovandermaas
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Some comments from my end. I still don't fully understand what these timers are that you need to halt. What do the timers represent? Number of cycles passed not in debug mode?
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| // Debug Mode output | ||
| assign debug_mode_o = debug_mode; |
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I see that debug mode is already exposed when RVFI is defined. Does that suffice in your use-case?
| // Debug Interface | ||
| input logic debug_req_i, | ||
| input logic debug_req_i, // Request to Core to enter debug mode | ||
| output logic debug_mode_o, // Indicates that the core has entered debug mode |
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You would need to add this anywhere where ibex_top is instantiated as well.
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This brings out a port called 'debug_mode_o' from the core and at the top, signifying the state of debug mode when IBEX is connected to other peripherals dependent on the debug mode to update their operation like halt, etc. No functional changes to it.