RAM delay in Simple system#2367
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marnovandermaas merged 2 commits intolowRISC:masterfrom Feb 6, 2026
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I just noticed you're merging this into master. We probably don't want to enable that 5-cycle delay by default ;)
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Yes, you're right. I'll make the default 0 and expose the delay as a FuseSoC parameter. |
This allows an extra delay to be added to the B-port of the RAM.
Add a parameter to Simple system to delay the instruction requests and expose this in the FuseSoC build instruction.
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The aim of this pull request is to make it possible to do bench-marking on Simple System where the instruction cache actually makes a difference. The RAM must thus respond with a delay on the instruction side.