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Merged
alex96295 merged 1 commit into from
Jul 9, 2023
Merged

fpga: Add flow and CI for implementation on VCU128 boards #75

alex96295 merged 1 commit into from
Jul 9, 2023

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@CyrilKoe CyrilKoe commented Jun 28, 2023 •
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Modifications :

  • hw : Added configuration to disable islands
  • target/xilinx : Added scripts, wrappers, constraints for VCU128 (tested) and ZCU102 (non tested)
  • target/xilinx/overrides : Some files were causing issues on the Vivado flow, I added comments there (not actual patches) in order not to open PRs everywhere. Is this a copyright issue? It can be removed before Carfield is open sourced.

Tests:

  • Host : Bitstream compiles, JTAG works
  • Host + Safety : Bitstream compiles, JTAG fails on the safety
  • Host + Safety + Pulp : Bitstream compiles
  • Host + Spatz : Bitstream compiles

Todo:

  • Add Yann's error slaves when disabling an island
  • Tests
  • Add support for VCU128'flash with opentitan's SPI driver and connection to external DDR4 (removed atm for simplicity of diffs).

This PR goes with the following MR
https://iis-git.ee.ethz.ch/carfield/carfield-nonfree/-/merge_requests/14

@CyrilKoe CyrilKoe requested a review from luca-valente as a code owner June 28, 2023 10:07
luca-valente
luca-valente reviewed Jun 28, 2023
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Very very nice, left some comments to define the best way to proceed 😄

@CyrilKoe CyrilKoe marked this pull request as draft June 30, 2023 13:15
@CyrilKoe CyrilKoe changed the title fpga: Added flow and CI for implementation on VCU128 boards (draft) fpga: Added flow and CI for implementation on VCU128 boards Jun 30, 2023
@CyrilKoe CyrilKoe force-pushed the fpga/pr1 branch 2 times, most recently from 2af6cd2 to 75819d8 Compare June 30, 2023 13:32
@alex96295 alex96295 changed the title (draft) fpga: Added flow and CI for implementation on VCU128 boards Draft: fpga: Added flow and CI for implementation on VCU128 boards Jul 2, 2023
@CyrilKoe CyrilKoe force-pushed the fpga/pr1 branch 3 times, most recently from 3398761 to ed32baa Compare July 4, 2023 11:39
@CyrilKoe CyrilKoe marked this pull request as ready for review July 4, 2023 15:57
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CyrilKoe commented Jul 4, 2023 •
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Ready to be reviewed @luca-valente @alex96295 @anga93 :)

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CyrilKoe commented Jul 4, 2023

Note the xdc split will be addressed in a next PR

@CyrilKoe CyrilKoe changed the title Draft: fpga: Added flow and CI for implementation on VCU128 boards fpga: Added flow and CI for implementation on VCU128 boards Jul 4, 2023
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Looks good to me, left only a minor comment

alex96295
alex96295 reviewed Jul 5, 2023
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alex96295
alex96295 reviewed Jul 5, 2023
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alex96295
alex96295 reviewed Jul 5, 2023
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alex96295
alex96295 reviewed Jul 5, 2023
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alex96295
alex96295 reviewed Jul 5, 2023
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alex96295
alex96295 reviewed Jul 5, 2023
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@alex96295 alex96295 changed the title fpga: Added flow and CI for implementation on VCU128 boards fpga: Add flow and CI for implementation on VCU128 boards Jul 5, 2023
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alex96295 commented Jul 5, 2023

I left few minor comments, great work!

I will merge in the next few days after you address what is left :)

@CyrilKoe CyrilKoe force-pushed the fpga/pr1 branch 2 times, most recently from d72d32c to 13cca0c Compare July 6, 2023 15:03
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fpga: Added flow and CI for implementation on VCU128 boards, added ov…
cfa86f2 
…erride files for Vivado compilation only

fpga: switched to xilinx.mk and removed non essential overrides

fpga: switched safety island bootmode and removed last override
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CyrilKoe commented Jul 6, 2023

Back to overriding tc_clk_xilinx until we discuss the tech_cells_generic case

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lgtm

@alex96295 alex96295 merged commit ba76551 into main Jul 9, 2023
@micprog micprog deleted the fpga/pr1 branch July 21, 2023 10:04
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