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set default=0 for DRACR, DRSR, IRACR, IRSR #212

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Merged
jonathanpallant merged 1 commit into from
Aug 4, 2026
Merged

set default=0 for DRACR, DRSR, IRACR, IRSR #212

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2 changes: 1 addition & 1 deletion aarch32-cpu/src/register/dracr.rs
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Expand Up @@ -5,7 +5,7 @@ use arbitrary_int::u3;
use crate::register::{SysReg, SysRegRead, SysRegWrite};

/// DRACR (*Data Region Access Control Register*)
#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
#[bitbybit::bitfield(u32, default = 0, debug, defmt_bitfields(feature = "defmt"))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct Dracr {
/// Execute Never
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2 changes: 1 addition & 1 deletion aarch32-cpu/src/register/drsr.rs
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Expand Up @@ -94,7 +94,7 @@ impl RegionSize {
}

/// DRSR (*Data Region Size and Enable Register*)
#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
#[bitbybit::bitfield(u32, default = 0, debug, defmt_fields(feature = "defmt"))]
pub struct Drsr {
/// Sub-region bitmask
///
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2 changes: 1 addition & 1 deletion aarch32-cpu/src/register/iracr.rs
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Expand Up @@ -5,7 +5,7 @@ use arbitrary_int::u3;
use crate::register::{SysReg, SysRegRead, SysRegWrite};

/// IRACR (*Instruction Region Access Control Register*)
#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
#[bitbybit::bitfield(u32, default = 0, debug, defmt_bitfields(feature = "defmt"))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct Iracr {
/// Execute Never
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2 changes: 1 addition & 1 deletion aarch32-cpu/src/register/irsr.rs
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Expand Up @@ -5,7 +5,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
pub use super::drsr::RegionSize;

/// IRSR (*Instruction Region Size and Enable Register*)
#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
#[bitbybit::bitfield(u32, default = 0, debug, defmt_fields(feature = "defmt"))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct Irsr {
/// Sub-region bitmask
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