Draft: explore LA57-aware virtual address validity - #599
Conversation
Add sealed fixed LA48, fixed LA57, and runtime virtual-address validity policies, with const construction for fixed-width addresses and runtime validation against CR4.LA57. Propagate address validity through the directly affected descriptor, interrupt, page, range, TLB, and register APIs while keeping existing four-level page-table traversal semantics explicit. Preserve the crate's Rust 1.59 configurations and architectural structure layouts, and add coverage for canonicality, arithmetic, conversions, and generic API behavior.
1. The
|
2. Types and functions that depend on
|
3. Prototype status and validationThe prototype implements all three validity models and propagates them widely enough to expose the affected API surface. It has been checked across the relevant feature, target, documentation, lint, and Rust 1.59 configurations. A branch of my own OS program builds against the current prototype and it works as expected. I would prefer to settle these questions before expanding the implementation to five-level page-table traversal. I am happy to revise the prototype in whichever direction reaches consensus. |
Purpose of this draft
This is a working prototype for LA57-aware virtual address types. It is meant to make the API choices and their effects reviewable in code, not to claim that all of those choices are final.
The work is inspired by #435 and #586. In particular, it agrees with the central idea in #586 that address validity should be represented by a generic parameter. It explores some additional questions that became visible while propagating that design through the crate and integrating it into my own OS program.
The current branch implements the runtime-valid-by-default end of the design space. That is useful as a prototype because it demonstrates what is required for a program to use the same address types while running in either LA48 or LA57 mode. It is not necessarily the best compatibility choice for the final API.
This PR is organized as a list of technical decisions. I have marked them as:
Scope
This prototype covers:
structures, basic page/range types, TLB operations, and register accessors;
It deliberately does not add P5 page-table traversal, P5 indices, or LA57 mapping support. Page-table APIs should be handled separately after the address model is settled. It also does not generalize
PhysAddr: LA57 changes virtual address canonicality, not the architectural physical-address width.