PerfOptCSRs

A microarchitecture for optimized RISC-V CSR access.

Overview

This repository contains the source files, build script and additional documentation associated with the primary solution developed in the paper: “High-Performance RISC-V CSR Access in FPGAs: Optimized Microarchitecture for Efficient Decoding and Multiplexing.” Specifically, this repository implements the DSPmux Default configuration, allowing exploration of the proposed optimized microarchitecture without requiring long and overly complex synthesis and implementation flows. The remaining configurations evaluated can be found here, to ensure full reproducibility of the experimental results reported in the publication.

The aim of this project was to implement and evaluate several microarchitectural strategies for improving the efficiency of Control and Status Register (CSR) access within a RISC-V processor core deployed on FPGA devices. These operations, though central to RISC-V system control and observability, can become a performance bottleneck in FPGA implementations due to the limited scalability of conventional LUT-based decoding and multiplexing schemes.

To address these limitations, this design adopts a hardware-aware heterogeneous aproach leveraging BRAM for CSR decoding, DSP slices for multiplexing operations, and LUTs, flip-flops and CARRY4 resources for optimized routing and control logic.

This architecture forms a minimal yet representative test environment that isolates CSR-related datapaths from the rest of the processor, enabling precise evaluation of different implementation strategies. The resulting designs demonstrate substantial improvements in performance, as well as area and power efficiency, achieving up to 250 MHz in the top-performing design while reducing logic utilization and dynamic power consumption. In particular, the configuration present in this repository results in a critical path of 5050 ps (198 MHz) with a relatively subdued implementation time (likely under 10 minutes on any computer from the last decade).

This project has been developed using Xilinx Vivado and targets the Nexys A7 board, featuring a Xilinx Artix-7 FPGA (xc7a100t-1csg324). Nevertheless, as discussed in greater depth in the article, these designs can generally be ported to other platforms with some work. In addition, the contents of this repository are organized to facilitate reproducibility and transparency of the results presented in the related publication.

Building the Project

To build the Vivado project from the provided sources:

1. Open Vivado (tested in version 2022.2).
2. In the Vivado TCL console, navigate to the directory containing the TCL script:

   cd <path_to_repository>

3. Source the TCL script to automatically create and build the project:

   source PerfOptCSRs-DSPmux_Default.tcl

This script will generate the Vivado project, add all necessary source files, apply the defined constraints, and configure the project appropriately. The process is fully automated and should reproduce the same build environment used in the article. Once finished, the project can be synthesized and implemented.

Notes on Reproducibility

To ensure reproducibility of experimental results, incremental compilation has been enabled by default. This setup relies on the provided Design Checkpoint (.dcp), which preserve the design’s netlist and implementation results. Consequently, when rebuilding the project, Vivado will re-use this checkpoint to generate an identical netlist to the one reported in the publication.

If you intend to modify or explore the design, you may wish to disable incremental compilation so that Vivado performs a clean synthesis and implementation of your modified sources. This can be done by adjusting the project settings within Vivado:

1. Open the Project Settings → Synthesis/Implementation tabs.

2. Locate the Incremental Compilation section.

3. Disable or modify the incremental options as appropriate.

Disabling this feature will allow Vivado to fully recompile the design from your modified HDL sources.