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87b76ca
first clean pass
May 1, 2020
61c82d2
Merge branch 'feat-non-generic' into feat-non-generic-cleanup-doc
pranav12321 Apr 15, 2021
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110 changes: 39 additions & 71 deletions src/peripherals_tm4c/adc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -3,24 +3,11 @@ use lc3_traits::peripherals::adc::{
AdcStateMismatch as StateMismatch,
};
extern crate tm4c123x;
use tm4c123x_hal::{Peripherals, prelude::*};
use tm4c123x::adc0;
use tm4c123x_hal::prelude::*;
use tm4c123x_hal::sysctl;

// ADC0_PC_R &= ~0xF; // 7) clear max sample rate field
// ADC0_PC_R |= 0x1; // configure for 125K samples/sec
// ADC0_SSPRI_R = 0x0123; // 8) Sequencer 3 is highest priority
// ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3
// ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger
// ADC0_SSMUX3_R &= ~0x000F; // 11) clear SS3 field
// ADC0_SSMUX3_R += 9; // set channel
// ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0
// ADC0_IM_R &= ~0x0008; // 13) disable SS3 interrupts
// ADC0_ACTSS_R |= 0x0008; // 14) enable sample sequencer 3

pub struct AdcShim {
states: PinArr<State>,
//components: Option<required_components>,
}

#[derive(Copy, Clone, Debug, PartialEq)]
Expand All @@ -29,7 +16,7 @@ pub enum State {
Disabled,
}

pub struct required_components{
pub struct RequiredComponents{
pub adc0: tm4c123x::ADC0,
pub adc1: tm4c123x::ADC1,
pub porte: tm4c123x::GPIO_PORTE,
Expand All @@ -51,7 +38,6 @@ impl Default for AdcShim {
fn default() -> Self {
Self {
states: PinArr([State::Disabled; Pin::NUM_PINS]),
//components: None,
}
}
}
Expand All @@ -60,42 +46,32 @@ impl Default for AdcShim {
pub struct SetError(StateMismatch);

impl AdcShim {
pub fn new(power: &tm4c123x_hal::sysctl::PowerControl, peripheral_set: required_components) -> Self {
pub fn new(power: &tm4c123x_hal::sysctl::PowerControl, peripheral_set: RequiredComponents) -> Self {

let mut ad0 = peripheral_set.adc0;
let mut ad1 = peripheral_set.adc1;
//let d = peripheral_set.porte.amsel;
let mut porte = peripheral_set.porte.split(power);
let porte_ams = unsafe { &*tm4c123x::GPIO_PORTE::ptr() };
porte_ams.dir.write(|w| unsafe{w.bits((porte_ams.dir.read().bits() & !0x003F ))});
porte_ams.afsel.write(|w| unsafe{w.bits((porte_ams.afsel.read().bits() | 0x003F ))});
porte_ams.den.write(|w| unsafe{w.bits((porte_ams.den.read().bits() & !0x003F ))});
porte_ams.amsel.write(|w| unsafe{w.bits((porte_ams.amsel.read().bits() | 0x003F ))});
porte_ams.dir.write(|w| unsafe{w.bits(porte_ams.dir.read().bits() & !0x003F )});
porte_ams.afsel.write(|w| unsafe{w.bits(porte_ams.afsel.read().bits() | 0x003F )});
porte_ams.den.write(|w| unsafe{w.bits(porte_ams.den.read().bits() & !0x003F )});
porte_ams.amsel.write(|w| unsafe{w.bits(porte_ams.amsel.read().bits() | 0x003F )});

let p = unsafe { &*tm4c123x::SYSCTL::ptr() };
// p.rcgcadc.write(|w| unsafe{w.bits(p.rcgcadc.read().bits() | 1)}); //activate adc0
// for pat in 0..100 {

// }
sysctl::control_power(
power, sysctl::Domain::Adc0,
sysctl::RunMode::Run, sysctl::PowerState::On);
sysctl::reset(power, sysctl::Domain::Adc0);
ad0.sspri.write(|w| unsafe{w.bits(0x0123)});
ad0.actss.write(|w| unsafe{w.bits((ad0.actss.read().bits() & !0x0008) )});
ad0.emux.write(|w| unsafe{w.bits((ad0.emux.read().bits() & !0xF000) )});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 9 ))});
ad0.actss.write(|w| unsafe{w.bits(ad0.actss.read().bits() & !0x0008)});
ad0.emux.write(|w| unsafe{w.bits(ad0.emux.read().bits() & !0xF000)});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 9 )});
ad0.ssctl3.write(|w| unsafe{w.bits(0x06)});
// ad0.pc.write(|w| unsafe{w.bits((ad0.pc.read().bits() & !0x0F) )});
// ad0.pc.write(|w| unsafe{w.bits((ad0.pc.read().bits() | 0x01) )});
// ad0.ssctl3.write(|w| unsafe{w.bits(0x06)});
// ad0.sspri.write(|w| unsafe{w.bits(0x0123)});
ad0.im.write(|w| unsafe{w.bits((ad0.im.read().bits() & !0x0008 ))});
ad0.im.write(|w| unsafe{w.bits(ad0.im.read().bits() & !0x0008 )});

Self{
states: PinArr([State::Disabled; Pin::NUM_PINS]),
//components: Some(peripheral_set),

}
}

Expand All @@ -119,29 +95,29 @@ impl Adc for AdcShim {
let x = usize::from(pin);
match x{
0 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 0 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 0 )});
}
1 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 1 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 1 )});
}
2 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 2 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 2 )});

}
3 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 3 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 3 )});
}
4 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 8 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 8 )});
}
5 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 9 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 9 )});
}


Expand All @@ -151,14 +127,13 @@ impl Adc for AdcShim {


}
ad0.actss.write(|w| unsafe{w.bits((ad0.actss.read().bits() | 0x0008 ))});
ad0.actss.write(|w| unsafe{w.bits(ad0.actss.read().bits() | 0x0008 )});


},
Disabled => {
self.states[pin] = State::Disabled;
let ad0 = unsafe { &*tm4c123x::ADC0::ptr() };
// ad0.actss.write(|w| unsafe{w.bits((ad0.actss.read().bits() & !0x0008 ))});
let ad0 = unsafe { &*tm4c123x::ADC0::ptr() };
},
};
Ok(())
Expand All @@ -168,13 +143,6 @@ impl Adc for AdcShim {
self.states[pin].into()
}

// ADC0_PSSI_R = 0x0008; // 1) initiate SS3
// while((ADC0_RIS_R&0x08)==0){}; // 2) wait for conversion done
// // if you have an A0-A3 revision number, you need to add an 8 usec wait here
// result = ADC0_SSFIFO3_R&0xFFF; // 3) read result
// ADC0_ISC_R = 0x0008; // 4) acknowledge completion
// return result;

fn read(&self, pin: Pin) -> Result<u8, ReadError> {
use State::*;
match self.states[pin] {
Expand All @@ -183,29 +151,29 @@ impl Adc for AdcShim {
let x = usize::from(pin);
match x{
0 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 0 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 0 )});
}
1 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 1 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 1 )});
}
2 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 2 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 2 )});

}
3 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 3 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 3 )});
}
4 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 8 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 8 )});
}
5 => {
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() & !0x000F ))});
ad0.ssmux3.write(|w| unsafe{w.bits((ad0.ssmux3.read().bits() + 9 ))});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() & !0x000F )});
ad0.ssmux3.write(|w| unsafe{w.bits(ad0.ssmux3.read().bits() + 9 )});
}


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