feat(multihart): add riscv isa extensions for multihart workloads

dts/README.md

@@ -99,10 +99,16 @@ python3 scripts/generate-xiangshan-multihart-dts.py \
 
 `--harts` must be in the range 2 through 128. The generator copies the CPU node for each hart,
 extends the CLINT, PLIC, and debug interrupt contexts, and applies the NEMU
-UARTLITE and PLIC settings. It normalizes every generated CPU to
-`riscv,isa = "rv64imafdc"`. Generated multi-hart templates reserve the fixed
+UARTLITE and PLIC settings. Generated multi-hart templates reserve the fixed
 131 MiB checkpoint window `[0x80300000, 0x88600000)`.
 
+The full capability block describes XiangShan hardware and is not fully
+emulated by the current QEMU `nemu` machine. In particular, DT-advertised
+`smrnmi` requires an OpenSBI platform `smrnmi_handlers_init` callback, while
+the `nemu` timer path cannot execute the DT-advertised `sstc` CSR sequence.
+The current multi-core DTB must omit `smrnmi` and `sstc` and run with
+`sstc=false`.
+
 The build does not invoke this generator automatically. Run it and review the
 result before building with the corresponding `HARTS` value.
 

dts/xiangshan-fpga-noAIA-2hart-mem8g.dts.in

@@ -43,7 +43,29 @@
 			 * workload template while using the FPGA board interrupt/peripheral
 			 * map below.
 			 */
-			riscv,isa = "rv64imafdc";
+			riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions =
+				"i", "m", "a", "f", "d", "c", "v", "h",
+				"sdtrig", "sha", "shcounterenw", "shgatpa",
+				"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
+				"shvstvecd", "smcsrind", "smdbltrp",
+				"smmpm", "smnpm", "smstateen",
+				"ss1p13", "ssccptr", "sscofpmf",
+				"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
+				"sspm", "ssstateen", "ssstrict",
+				"sstvala", "sstvecd", "ssu64xl", "supm",
+				"sv39", "sv48", "svade", "svbare", "svinval",
+				"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
+				"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
+				"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
+				"zic64b",
+				"ziccamoa", "ziccif", "zicclsm", "ziccrse",
+				"zicntr", "zicond", "zicsr", "zifencei",
+				"zihintntl", "zihintpause", "zihpm", "zimop",
+				"zkn", "zknd", "zkne", "zknh", "zksed",
+				"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
+				"zvkt", "zvl128b", "zvl32b", "zvl64b";
 			riscv,cbom-block-size = <0x40>;
 			riscv,cboz-block-size = <0x40>;
 
@@ -82,7 +104,29 @@
 			 * workload template while using the FPGA board interrupt/peripheral
 			 * map below.
 			 */
-			riscv,isa = "rv64imafdc";
+			riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions =
+				"i", "m", "a", "f", "d", "c", "v", "h",
+				"sdtrig", "sha", "shcounterenw", "shgatpa",
+				"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
+				"shvstvecd", "smcsrind", "smdbltrp",
+				"smmpm", "smnpm", "smstateen",
+				"ss1p13", "ssccptr", "sscofpmf",
+				"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
+				"sspm", "ssstateen", "ssstrict",
+				"sstvala", "sstvecd", "ssu64xl", "supm",
+				"sv39", "sv48", "svade", "svbare", "svinval",
+				"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
+				"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
+				"zbs", "zca", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
+				"zic64b",
+				"ziccamoa", "ziccif", "zicclsm", "ziccrse",
+				"zicntr", "zicond", "zicsr", "zifencei",
+				"zihintntl", "zihintpause", "zihpm", "zimop",
+				"zkn", "zknd", "zkne", "zknh", "zksed",
+				"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
+				"zvkt", "zvl128b", "zvl32b", "zvl64b";
 			riscv,cbom-block-size = <0x40>;
 			riscv,cboz-block-size = <0x40>;